參數(shù)資料
型號: M65676FP
廠商: Mitsubishi Electric Corporation
英文描述: DIGITAL NTSC/PAL ENCODER
中文描述: 數(shù)字的NTSC / PAL編碼器
文件頁數(shù): 16/17頁
文件大?。?/td> 83K
代理商: M65676FP
MITSUBISHI ICs (TV)
M65675FP/M65676FP
DIGITAL NTSC/PAL ENCODER
16
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
The pixel data interface pin assignment is shown in Table 1.
Table 1 Pixel Data Interface Pin Assignment
Note1 : In CCIR656 mode, H sync and V sync generated by EAV will be output via terminals HD and VD, respectively.
Pin name
I/O
Function
PXCLK
O
Pixel clock output.
In the case of CCIR656 / CCIR601 8-bit data and CCIR601 16-bit inputs, this will be a free-run clock of 27MHz and
13.5MHz, respectively.
Horizontal sync signal. Input in the slave or output in the master mode.
Vertical sync signal. Input in the slave or output in the master mode.
Pixel data input.
8-bit data input in CCIR656 / CCIR601 or the color differential signals (Cb/Cr) input in CCIR601 16-bit data format.
Pixel data input.
Luma (Y) data input in CCIR601 16-bit data format.
HD
(Note1)
VD
(Note1)
I/O
I/O
PXD [7:0]
I
PD [7:0]
I
OSD Interface
The OSD data, which are storaged in the address assigned by the
color look-up table RAM (CLT-RAM) address data input via OSD
[2:0] ports, are multiplexed into the Y signal synchronizing with OSD
clock (OSDCK) delivered from the M65675FP/M65676FP.
The OSD interface pin assignment is shown in Table 2.
Table 2 The OSD interface Pin assignment
Pin name
I/O
Function
OSDCK
O
OSD clock output.
13.5MHz free-run clock or 6.25MHz H-start-and-stop clock.
Color look-up table RAM address input.
OSD [2:0]
I
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