參數(shù)資料
型號(hào)： M65676FP
廠商： Mitsubishi Electric Corporation
英文描述： DIGITAL NTSC/PAL ENCODER
中文描述： 數(shù)字的NTSC / PAL編碼器
文件頁(yè)數(shù)： 15/17頁(yè)
文件大小： 83K
代理商： M65676FP
MITSUBISHI ICs (TV)
M65675FP/M65676FP
DIGITAL NTSC/PAL ENCODER
15
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
DESCRIPTION OF PIN
(cont.)
Pin No.
Pin name
Type
Function
42
Ccomp
I
Phase compensation for chroma or V D/A converters.
It should be connected to the analog ground via a capacitor.
Chroma or V signal output.
It should be connected to the analog supply via a resistor (RL).
The output amplitude is set up by reference resistor (Rref) and RL.
Supply Analog positive supply for D/A converters.
Supply Analog ground for D/A converters.
Luma or V signal output.
It should be connected to the analog supply via a resistor (RL).
The output amplitude is set up by reference resistor (Rref) and RL.
Reference current control for chroma or V D/A converter.
It should be connected to the analog supply via a reference resistor (Rref).
Reference current control for luma or U D/A converter.
It should be connected to the analog supply via a reference resistor (Rref).
Phase compensation for luma or U D/A converters.
It should be connected to the analog ground via a capacitor.
No connection.
Supply Digital positive power supply for internal logic.
Supply Digital ground for internal logic.
System clock output.
It should be in no connection except that it is connected to a X'tal oscillator.
System clock input.
The clock frequency is 27.0MHz only.
Supply Digital ground for I/O.
43
DAC
O
44
45
AV
DD1
AV
SS1
46
DAY
O
47
Cref
I
48
Yref
I
49
Ycomp
I
50
51
52
N.C.
DV
DD1
DV
SS1
53
Xout
O
54
Xin
I
55
56
57
58
59
60
61
62
63
64
DV
SS2
PXD7
PXD6
PXD5
PXD4
PXD3
PXD2
PXD1
PXD0
DV
DD2
I
Pixel data inputs.
The acceptable video data are;
multiplexed video data (Y/Cb/Cr) including timing reference code of SAV and EAV as defined in
CCIR Rec656, and multiplexed video data (Y/Cb/Cr) as defined in CCIR Rec601, and multiplexed
Color difference signals (Cb/Cr).
An MSB and LSB is PXD7 and PXD0, respectively.
Supply Digital positive power supply for I/O
Interface
The M65675FP/M65676FP has two interfaces as follows;
Pixel data interface
OSD interface
Pixel Data Interface
The M65675FP/M65676FP accepts these 6 digital pixel data
formats as shown below;
In CCIR656
Y and Cb/Cr, in a digital video transmission format
Y and U/V, in a time multiplexed 8-bit serial data format
In CCIR601
Y and Cb/Cr, in a digital video transmission format
Y and U/V, in a time multiplexed 8-bit serial data format
Y, in a digital video transmission format and time multiplexed
Cb/Cr
Y and U/V, in a time multiplexed 16-bit serial data format
The 8-bit serial data in CCIR656 and CCIR601 are taken into the
M65675FP/M65676FP through PXDATA [7:0] ports synchronizing
with a pixel clock (PXCLK) generated by the LSI. In the case of
CCIR601 16-bit serial data, 8-bit color difference signals (Cb/Cr or
U/V) and luma signal (Y) are taken into the LSI synchronizing with
pixel clock (PXCLK) through PXD [7:0] and VD [7:0] port,
respectively.
CCIR656 pixel data are accepted in only the slave mode, while
CCIR601 ones are accepted in both the master and slave modes.
In the case of CCIR656 pixel data, H/V sync and a field
identification signals are regenerated internally referring to SAV and
EAV code multiplexed in the pixel data. In the case of CCIR601
pixel data, H/V sync and the field identification signals are
regenerated internally, then the H and V sync signals are available
via HD and VD ports in the master mode operation, respectively.
Moreover, in the slave mode, the M65675FP/M65676FP is in the
slave operation synchronized with H/V sync signals via HD/VD
ports and a field identification is done using the H/V sync input
signals.
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