參數(shù)資料
型號(hào)： M5M4V16169DRT-15
廠商： Mitsubishi Electric Corporation
英文描述： 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
中文描述： 16MCDRAM：16米（100萬字由16位）與16K的緩存內(nèi)存（1024字由16位）的SRAM
文件頁(yè)數(shù)： 10/64頁(yè)
文件大?。?/td> 737K
代理商： M5M4V16169DRT-15
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MODE DESCRIPTIONS (3)
MITSUBISHI LSIs
(REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
Buffer Read
Transfer &
SRAM Read
Buffer Write
Transfer &
SRAM Write
Data is transferred from the Read Buffer (RB2) to the SRAM, and simultaneously, data (16
bit word) is read from the RB2 to the I/O pins. Addresses As3-9 select the SRAM Row to
which the 8X16 bit block is to be written. Addresses As0-As2 decode the 16-bit word to be
read.
Data is first written from the I/O pins to SRAM as decoded by As0-As9. Then, the SRAM
Row (=Block) decoded by As3-As9 is transferred to the Write-Buffer1 (WB1). The Buffer
Write Transfer cycle "clears" all transfer mask bits in the WB1 Mask (allowing all data to be
transferred in a successive DRAM Write Transfer cycle). DQCu and DQCl control Upper
and Lower byte writes respectively, however all transfer mask bits in the WB1 are cleared.
10
X
DQs
SRAM
1KX16
8X16
8X16
8X16
8X16
8X16
16bits
16bits
16bits
As3-9
1of128Decode
SRAM RowDecoder
DRAM
1M X 16
Ad0-11
1of4096Decode
Ad3-7
1of32
Decode
As0-2
As0-2
1of8Decode
8X16Block
8X16Block
WB1
Upper Byte
Lower Byte
Upper Byte
Lower Byte
DRAM RowDecoder
16bits
As0-2
1of8Decode
Upper Byte
Lower Byte
Upper Byte
Lower Byte
X
DQs
SRAM
1KX16
8X16
8X16
8X16
8X16
8X16
16bits
16bits
16bits
As3-9
1of128Decode
SRAM RowDecoder
DRAM
1M X 16
Ad0-11
1of4096Decode
Ad3-7
1of32
Decode
As0-2
1of8
Decode
As0-2
1of8Decode
8X16Block
8X16Block
Upper Byte
Lower Byte
DRAM RowDecoder
16bits
As0-2
1of8Decode
Lower Byte
RB2
Lower Byte
RB1
RB1
RB2
Upper Byte
Lower Byte
WB1
DQ8-15
DQ0-7
DQ8-15
DQ0-7
相關(guān)PDF資料
PDF描述
M5M4V16169DRT-7 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
M5M4V16169DRT-8 22182053
M5M4V16G50DFP-10 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
M5M4V16G50DFP-12 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
M5M4V16G50DFP-8 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M5M4V16169DRT-7 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
M5M4V16169DRT-8 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
M5M4V16169DTP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
M5M4V16169DTP-10 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
M5M4V16169DTP-15 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
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