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參數(shù)資料
| 型號： | M59BW102N |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 1 Mbit 64Kb x16, Burst Low Voltage Flash Memory |
| 中文描述： | 1兆位64Kb的x16插槽，突發(fā)低電壓快閃記憶體 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 181K |
| 代理商： | M59BW102N |
M59BW102
8/24
Table 8. Status Register Bits
Note: Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
DQ
Name
Logic Level
Definition
Note
7
Data
Polling
’1’
Erase Complete
Indicates the P/E.C. status, check during
Program or Erase, and on completion before
checking bits DQ5 for Program or Erase
Success.
’0’
Erase On-going
DQ
Program Complete
DQ
Program On-going
6
Toggle Bit
’-1-0-1-0-1-0-1-’
Erase or Program On-going
Successive reads output complementary
data on DQ6 while Programming or Erase
operations are on-going. DQ6 remains at
constant level when P/E.C. operations are
completed.
DQ
Program Complete
’-1-1-1-1-1-1-1-’
Erase Complete
5
Error Bit
’1’
Program or Erase Error
This bit is set to ’1’ in the case of
Programming or Erase failure.
’0’
Program or Erase On-going
4
Reserved
3
Erase
Time Bit
’1’
Erase Timeout Period Expired P/E.C. Erase operation has started.
’0’
Erase Timeout Period On-
going
2
Toggle Bit
’-1-0-1-0-1-0-1-’
Chip Erase
Indicates the erase status.
’1’
Program On-going or Erase
Complete
1
Reserved
0
Reserved
Instructions
See Table 7.
Read/Reset (RD) Instruction.
The Read/Reset
instruction consists of one write cycle giving the
command F0h. It can be optionally preceded by
the two Coded cycles. Subsequent read opera-
tions will read the memory array addressed and
output the data read. Read/Reset is not accepted
in Program/Erase operation unless a fail occurred.
Auto Select (AS) Instruction.
This
uses the two Coded cycles followed by one write
cycle giving the command 90h to address 555h for
command set-up. A subsequent read will output
the manufacturer code and the device code de-
pending on the levels of A0 and A1. The manufac-
turer code, 20h, is output when the addresses
instruction
lines A0 and A1 are Low, the device code, C1h is
output when A0 is High with A1 Low.
Program (PG) Instruction.
This instruction uses
four write cycles. The Program command A0h is
written to address 555h on the third cycle after two
Coded cycles. A fourth write operation latches the
Address on the falling edge of W or E and the Data
to be written on the rising edge and starts the P/
E.C. Read operations output the Status Register
bits after the programming has started. Memory
programming is made only by writing ’0’ in place of
’1’. Status bits DQ6 and DQ7 determine if pro-
gramming is on-going and DQ5 allows verification
of any possible error.
Chip Erase (CE) Instruction.
This instruction uses
six write cycles. The Set-up command 80h is writ-
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