參數(shù)資料
型號(hào)： M58WR064HU70ZB6U
元件分類： PROM
英文描述： 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA44
封裝： 7.70 X 9 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFBGA-44
文件頁數(shù)： 54/117頁
文件大?。?/td> 2300K
代理商： M58WR064HU70ZB6U
M58WR064HU M58WR064HL
Configuration Register
41/117
8
Configuration Register
The Configuration Register is used to configure the type of bus access that the memory will
perform. Refer to Section 9: Read modes for details on read operations.
The Configuration Register is set through the Command Interface. After a Reset or Power-
Up the device is configured for asynchronous read (CR15 = 1). The Configuration Register
bits are described in Table 10. They specify the selection of the burst length, burst type,
burst X latency and the Read operation. Refer to Figures 6 and 7 for examples of
synchronous burst configurations.
8.1
Read Select Bit (CR15)
The Read Select bit, CR15, is used to switch between asynchronous and synchronous Bus
Read operations. When the Read Select bit is set to ’1’, read operations are asynchronous;
when the Read Select bit is set to ’0’, read operations are synchronous. Synchronous Burst
Read is supported in both parameter and main blocks and can be performed across banks.
On reset or power-up the Read Select bit is set to’1’ for asynchronous access.
8.2
Bus Invert Configuration (CR14)
The Bus Invert Configuration bit is used to enable the BINV functionality. When the
functionality is enabled, if the BINV pin operates as an input pin (during write bus
operations), the BINV signal must always be driven; if it operates as an output pin (during
read bus operations), the functionality is valid only during synchronous read operations.
8.3
X-Latency Bits (CR13-CR11)
The X-Latency bits are used during Synchronous Read operations to set the number of
clock cycles between the address being latched and the first data becoming available. Refer
For correct operation the X-Latency bits can only assume the values in Table 10:
Table 9 shows how to set the X-Latency parameter, taking into account the speed class of
the device and the Frequency used to read the Flash memory in Synchronous mode.
Table 9.
X-Latency Settings
fmax
tKmin
X-Latency min
Speed 70ns
30MHz
33ns
2
40MHz
25ns
3
54MHz
19ns
4
66MHz
15ns
4
相關(guān)PDF資料
PDF描述
M59DR032F100N1T 2M X 16 FLASH 1.8V PROM, 100 ns, PDSO48
M5F7924 24 V FIXED NEGATIVE REGULATOR, PSFM3
M5F7920 20 V FIXED NEGATIVE REGULATOR, PSFM3
M5F7918 18 V FIXED NEGATIVE REGULATOR, PSFM3
M5F7915 15 V FIXED NEGATIVE REGULATOR, PSFM3
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M58WR064KB70ZB6E 制造商:Micron Technology Inc 功能描述:WIRELESS FLASH VFBGA 7.7X9.0X1.0 56 8X7 0.75 - Trays 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 70NS 56VFBGA
M58WR064KB70ZB6F 制造商:Micron Technology Inc 功能描述:FLASH 28F640W18TD 60 VF-PBGA56 SB48 EX - Tape and Reel
M58WR064KB70ZB6F TR 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 70NS 56VFBGA
M58WR064KB7AZB6E 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 70NS 56VFBGA
M58WR064KB7AZB6F 制造商:Micron Technology Inc 功能描述:WIRELESS - Tape and Reel
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