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參數(shù)資料
| 型號： | M58WR064HU70ZB6U |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA44 |
| 封裝： | 7.70 X 9 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFBGA-44 |
| 文件頁數(shù)： | 113/117頁 |
| 文件大?。?/td> | 2300K |
| 代理商： | M58WR064HU70ZB6U |
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M58WR064HU M58WR064HL
Common Flash Interface
95/117
Table 38.
Protection Register information
Offset
Data
Description
Value
(P+E)h = 47h
0001h
Number of protection register fields in JEDEC ID space.
0000h indicates that 256 fields are available.
1
(P+F)h = 48h
0080h Protection Field 1: Protection Description
Bits 0-7 Lower byte of protection register address
Bits 8-15 Upper byte of protection register address
Bits 16-23 2n bytes in factory pre-programmed region
Bits 24-31 2n bytes in user programmable region
0080h
(P+10)h = 49h
0000h
(P+11)h = 4Ah
0003h
8 Bytes
(P+12)h= 4Bh
0004h
16 Bytes
Table 39.
Burst read information
Offset
Data
Description
Value
(P+13)h = 4Ch
0003h
Page-mode read capability
bits 0-7’n’ such that 2n HEX value represents the number of
read-page bytes. See offset 28h for device word width to
determine page-mode data output width.
8 Bytes
(P+14)h = 4Dh
0004h
Number of synchronous mode read configuration fields that
follow.
4
(P+15)h = 4Eh
0001h
Synchronous mode read capability configuration 1
bit 3-7 Reserved
bit 0-2 ’n’ such that 2n+1 HEX value represents the maximum
number of continuous synchronous reads when the device is
configured for its maximum word width. A value of 07h
indicates that the device is capable of continuous linear
bursts that will output data until the internal burst counter
reaches the end of the device’s burstable address space.
This field’s 3-bit value can be written directly to the read
configuration register bit 0-2 if the device is configured for its
maximum word width. See offset 28h for word width to
determine the burst data output width.
4
(P+16)h = 4Fh
0002h
Synchronous mode read capability configuration 2
8
(P+17)h = 50h
0003h
Synchronous mode read capability configuration 3
16
(P+18)h = 51h
0007h
Synchronous mode read capability configuration 4
Cont.
Table 40.
Bank and erase block region information(1) (2)
1. The variable P is a pointer which is defined at CFI offset 15h.
2. Bank Regions. There are two Bank Regions, see Appendix A, Table 31 and Table 32
M58WR064HU
M58WR064HL
Description
Offset
Data
Offset
Data
(P+19)h = 52h
02h
(P+19)h = 52h
02h
Number of Bank Regions within the device
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M58WR064KB70ZB6E | 制造商:Micron Technology Inc 功能描述:WIRELESS FLASH VFBGA 7.7X9.0X1.0 56 8X7 0.75 - Trays 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 70NS 56VFBGA |
| M58WR064KB70ZB6F | 制造商:Micron Technology Inc 功能描述:FLASH 28F640W18TD 60 VF-PBGA56 SB48 EX - Tape and Reel |
| M58WR064KB70ZB6F TR | 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 70NS 56VFBGA |
| M58WR064KB7AZB6E | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 70NS 56VFBGA |
| M58WR064KB7AZB6F | 制造商:Micron Technology Inc 功能描述:WIRELESS - Tape and Reel |
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