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Figure 13. Asynchronous Latch Controlled Bus Read AC Waveforms
Note: Asynchronous Read (M15 = 1), Latch Enable Controlled (M3 = 1)
Table 18. Asynchronous Latch Controlled Bus Read AC Characteristics
Note: For other timings see Table
17, Asynchronous Bus Read Characteristics.
Symbol
Parameter
Test Condition
M58LW128
Unit
150
tAVLL
Address Valid to Latch Enable Low
E = VIL
Min
0
ns
tAVLH
Address Valid to Latch Enable High
E = VIL
Min
10
ns
tLHLL
Latch Enable High to Latch Enable Low
Min
10
ns
tLLLH
Latch Enable Low to Latch Enable High
E = VIL
Min
10
ns
tELLL
Chip Enable Low to Latch Enable Low
Min
0
ns
tELLH
Chip Enable Low to Latch Enable High
Min
10
ns
tLLQX
Latch Enable Low to Output Transition
E = VIL, G = VIL
Min
0
ns
tLLQV
Latch Enable Low to Output Valid
E = VIL, G = VIL
Min
150
ns
tLHAX
Latch Enable High to Address Transition
E = VIL
Min
10
ns
tGLQX
Output Enable Low to Output Transition
E = VIL
Min
0
ns
tGLQV
Output Enable Low to Output Valid
E = VIL
Max
20
ns
tEHLX
Chip Enable High to Latch Enable Transition
Min
0
ns
AI06132b
L
E
G
A1-A23
DQ0-DQx
VALID
tEHLX
tLHLL
tLHAX
tAVLL
tELLL
tLLLH
tEHQX
tGHQZ
tLLQV
tGLQV
OUTPUT
tAVLH
tELLH
tGHQX
tLLQX
tEHQZ
tGLQX