23/53
M58LW064A, M58LW064B
Set Burst Configuration Register (SBCR).
This instruction uses two command cycles. The
Burst ConfigurationSetup command 60h is written
with the address corresponding to the Set Burst
Configuration Register content. Then in the sec-
ond write cycle the address bus A2-A17 specifies
the BCR, Burst Configuration Register, informa-
tion and the command 03h. The burst length, type,
latency, synchronous/asynchronous read mode
and clock edge active configuration are defined in
that operation. After the command 03h the device
will default in the Read array mode.
Status Register Bits.
The P/E.C. status is indi-
cated during execution with a Ready/Busy output
available on DQ7. Any read attempt during Pro-
gram or Erase command execution will automati-
cally update the Status Register bits. The P/E.C.
automatically sets bits DQ1, DQ2, DQ4, DQ5,
DQ6 and DQ7. The bit DQ0 is reserved for future
use and should be masked. It is not necessary to
specify an address when the Status Register bits
are read. The Status Register is a static memory
register that is reset when RP signalis active or on
a power-down operation.
POWER SUPPLY
Power Down.
The memory provides Reset/Pow-
er-down control using the input RP. When Reset/
Power-down RP is pulled to VIL the supply current
drops totypically less than 1
μ
A, the memory isde-
selected and the outputs are at high impedance. If
RP is pulled to V
IL
during a Program or Erase op-
eration, this operation is aborted after a latency
time of t
PLRH
and the memory content is nolonger
valid.
RESET, POWER-DOWN AND POWER-UP
See Fig 16.
The device is reset if the Reset/Power-down RP
input is pulled to V
IL
for longer than tPLPH. If the
device was in a Read mode then it will recover
from reset after a time of t
PHQV
to give valid data
output. If the device was executing an Erase or
Program operation, with the P/E.C. active, the op-
eration will abort in a time of t
PLRH
maximum. The
device will be ready to accept new write com-
mends after a time of t
PHWL
or t
PHEL
.
The supply voltages V
DD
and V
DDQ
must be high
a timet
VDHEL
or t
VDHWL
before a read or write cy-
cle. At firstpower up Reset/Power-down should be
held Low for a time of t
VDHPH
after V
DD
and V
DDQ
are high. The device willbe ready to accept its first
read or write commands after a time of t
PUR
or
t
PUW
.
COMMON FLASH INTERFACE - CFI
The introduction to the JEDEC CFI specification
Rel. 1.2 quotes, ”The Common Flash Interface
(CFI) specification outlines a device and host sys-
tem software interrogation handshake which al-
lows specific software algorithms to be used for
entire families of devices. This allows device-inde-
pendent, JEDEC, ID independent and forward-
and backward-compatible software support for the
specified flash device families. It allows flash ven-
dors to standardize their existing interfaces for
long-term compatibility.”
The CFI Query instructionRCFIdescribes how the
device enters the CFI Query mode which enables
information tobe read from the Flash memory. CFI
allows a system software to query the flash device
to determine various electrical and timing parame-
ters, density information and functions supported
by the device. CFI allows the system to easily in-
terface to the flash memory, to learn about its fea-
tures and parameters, enabling the software to
upgrade itself when necessary.
Query Structure Overview
The flash memory displays the CFI data structure
when the CFI Query Instruction RCFI is issued. A
list of the main subsections is detailed in Tables 15
to 19.