- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25618 > M54HC112D1 (STMICROELECTRONICS) HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16 PDF資料下載
參數(shù)資料
| 型號： | M54HC112D1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 鎖存器 |
| 英文描述： | HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 275K |
| 代理商： | M54HC112D1 |
Obsolete
Product(s)
- Obsolete
Product(s)
Obsolete
Product(s)
- Obsolete
Product(s)
M54HC112
5/11
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr =tf =6ns)
CAPACITIVE CHARACTERISTICS
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) =CPD xVCC xfIN +ICC/2 (per FLIP/
FLOP)
Symbol
Parameter
Test Condition
Value
Unit
VCC
(V)
TA = 25°C
-40 to 85°C
-55 to 125°C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
tTLH tTHL Output Transition
Time
2.0
30
75
95
110
ns
4.5
8
15
19
22
6.0
7
13
16
19
tPLH tPHL Propagation Delay
Time (CK -Q, Q)
2.0
52
125
155
190
ns
4.5
16
25
31
38
6.0
14
21
26
32
tPLH tPHL Propagation Delay
Time (CLR,PR -Q,
Q)
2.0
68
135
170
205
ns
4.5
17
27
34
41
6.0
14
23
29
35
fMAX
Maximum Clock
Frequency
2.0
8
16
6.4
5.4
MHz
4.5
40
683227
6.0
47
793832
tW(H)
tW(L)
Minimum Pulse
Width (CLOCK)
2.0
20
75
95
110
ns
4.5
5
15
19
22
6.0
4
13
16
19
tW(L)
Minimum Pulse
Width (CLR,PR)
2.0
20
75
95
110
ns
4.5
5
15
19
22
6.0
4
13
16
19
ts
Minimum Set-up
Time
2.0
28
75
95
110
ns
4.5
7
15
19
22
6.0
6
13
16
19
th
Minimum Hold
Time
2.0
0
ns
4.5
0
6.0
0
tREM
Minimum Removal
Time (CLR,PR)
2.0
24
50
60
70
ns
4.5
4
10
12
14
6.0
3
9
10
12
Symbol
Parameter
Test Condition
Value
Unit
VCC
(V)
TA = 25°C
-40 to 85°C
-55 to 125°C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
CIN
Input Capacitance
5.0
5
10
pF
CPD
Power Dissipation
Capacitance (note
1)
5.0
33
pF
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M54HC11K1 | HC/UH SERIES, TRIPLE 3-INPUT AND GATE, CDFP14 |
| M54HC138K1 | HCT SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, CDFP16 |
| M54HC175K | HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16 |
| M54HC240K1 | HC/UH SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, CDFP20 |
| M54HC273K | HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDFP20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M54HC112F1R | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DUAL J-K FLIP FLOP WITH PRESET AND CLEAR |
| M54HC112K | 制造商:STMicroelectronics 功能描述:LOGIC, 5VOLTSFLIP FLOPDUAL J-K FF + PRESET + CLEARFLAT-16 SO - Bulk |
| M54HC112K1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR |
| M54HC113 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DUAL J-K FLIP FLOP WITH PRESET |
| M54HC113F1R | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DUAL J-K FLIP FLOP WITH PRESET |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。