參數(shù)資料
型號: M54HC175K
廠商: STMICROELECTRONICS
元件分類: 鎖存器
英文描述: HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16
封裝: CERAMIC, DFP-16
文件頁數(shù): 1/10頁
文件大?。?/td> 267K
代理商: M54HC175K
1/10
April 2004
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HIGH SPEED:
tPD =16ns (TYP.) at VCC =6V
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LOW POWER DISSIPATION:
ICC =4A(MAX.) at TA=25°C
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HIGH NOISE IMMUNITY:
VNIH =VNIL = 28% VCC (MIN.)
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SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|= IOL =4mA (MIN)
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BALANCED PROPAGATION DELAYS:
tPLH tPHL
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WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
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PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 175
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SPACE GRADE-1: ESA SCC QUALIFIED
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50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
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NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
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DEVICE FULLY COMPLIANT WITH
SCC-9203-052
DESCRIPTION
The M54HC175 is an high speed CMOS HEX
D-TYPE FLIP FLOP WITH CLEAR fabricated with
silicon gate C2MOS technology.
These four flip-flops are controlled by a clock input
(CLOCK) and a clear input (CLEAR). The
information data applied to the D inputs (1D to 4D)
are transferred to the outputs (1Q to 4Q and 1Q to
4Q) on the positive-going edge of the clock pulse.
The reset function is accomplished when the
CLEAR input is low and all Q outputs are low
regardless of other input conditions.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M54HC175
RAD-HARD QUAD D-TYPE FLIP FLOP WITH CLEAR
PIN CONNECTION
ORDER CODES
PACKAGE
FM
EM
DILC
M54HC175D
M54HC175D1
FPC
M54HC175K
M54HC175K1
DILC-16
FPC-16
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