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參數(shù)資料
| 型號： | M52D128168A |
| 廠商： | Elite Semiconductor Memory Technology Inc. |
| 英文描述： | 2M x 16 Bit x 4 Banks Synchronous DRAM |
| 中文描述： | 200萬× 16位× 4個(gè)銀行同步DRAM |
| 文件頁數(shù)： | 43/47頁 |
| 文件大?。?/td> | 1209K |
| 代理商： | M52D128168A |
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ES MT
Preliminary
M52D128168A
Elite Semiconductor Memory Technology Inc.
Revision
:
1.0
Publication Date
:
May. 2007
43/47
Self Refresh Entry & Exit Cycle
*
Note :
TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
cf.) Once the device enters self refresh mode, minimum t
RAS
is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum t
RFC
is required after CKE going high to complete self refresh exit.
7. Burst auto refresh is required before self refresh entry and after self refresh exit if the
system uses burst refresh.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M52D128168A-10BG | 2M x 16 Bit x 4 Banks Synchronous DRAM |
| M52D128168A-10TG | 2M x 16 Bit x 4 Banks Synchronous DRAM |
| M52D128168A-7.5BG | 2M x 16 Bit x 4 Banks Synchronous DRAM |
| M52D128168A-7.5TG | 2M x 16 Bit x 4 Banks Synchronous DRAM |
| M52D16161A | 512K x 16Bit x 2Banks Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M52D128168A_09 | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Mobile Synchronous DRAM |
| M52D128168A_1 | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM |
| M52D128168A-10BG | 制造商:ELITE SEMICONDUCTOR 功能描述:SDRAM 128MB 1.8V 100MHZ FBGA54 |
| M52D128168A-10BIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM |
| M52D128168A-10TG | 制造商:ELITE SEMICONDUCTOR 功能描述:SDRAM 128MB 1.8V 100MHZ TSOPII54 |
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