參數(shù)資料
型號(hào): M52D128168A
廠商: Elite Semiconductor Memory Technology Inc.
英文描述: 2M x 16 Bit x 4 Banks Synchronous DRAM
中文描述: 200萬(wàn)× 16位× 4個(gè)銀行同步DRAM
文件頁(yè)數(shù): 25/47頁(yè)
文件大?。?/td> 1209K
代理商: M52D128168A
ES MT
10. Clock Suspend Exit & Power Down Exit
1) Cl o c k S u s p en d ( = Ac t i v e P ow er D o wn ) E x i t
Preliminary
M52D128168A
Elite Semiconductor Memory Technology Inc.
Revision
:
1.0
Publication Date
:
May. 2007
25/47
11. Auto Refresh & Self Refresh
*Note
:
1. Active power down : one or more banks active state.
2. Precharge power down : all banks precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after auto refresh command.
During t
RFC
from auto refresh command, any other command can not be accepted.
4. Before executing auto/self refresh command, all banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh entry, refresh interval and refresh operation are performed internally.
After self refresh entry, self refresh mode is kept while CKE is low.
During self refresh entry, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.
For the time interval of t
RFC
from self refresh exit command, any other command can not be accepted.
CLK
CKE
Internal
CLK
C M D
R D
t
S S
*Not e 1
CLK
CKE
Internal
CLK
C M D
AC T
t
S S
*Not e 2
NOP
2) P ow er D ow n ( = P r ec h a r g e P o we r Do wn )
CLK
CMD
PRE
AR
CKE
CMD
t
RP
t
RF C
* Not e 5
* N ot e4
CLK
CMD
PRE
SR
CKE
CMD
t
R P
t
R F C
* N ot e4
1) A u t o Re f r es h & S e lf R ef r e s h
2 ) S el f Re f r es h
* N ot e3
* N ot e6
相關(guān)PDF資料
PDF描述
M52D128168A-10BG 2M x 16 Bit x 4 Banks Synchronous DRAM
M52D128168A-10TG 2M x 16 Bit x 4 Banks Synchronous DRAM
M52D128168A-7.5BG 2M x 16 Bit x 4 Banks Synchronous DRAM
M52D128168A-7.5TG 2M x 16 Bit x 4 Banks Synchronous DRAM
M52D16161A 512K x 16Bit x 2Banks Synchronous DRAM
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