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參數(shù)資料
| 型號： | M50FW040NB5TP |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 4-Mbit (512 Kb x8, uniform block) 3-V supply firmware hub Flash memory |
| 中文描述： | 4兆位（512 KB的× 8，均勻塊）3 - V電源供電的閃存固件樞紐 |
| 文件頁數(shù)： | 17/53頁 |
| 文件大小： | 278K |
| 代理商： | M50FW040NB5TP |
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M50FW040
Bus operations
17/53
3
Bus operations
The two interfaces have similar bus operations but the signals and timings are completely
different. The Firmware Hub (FWH) Interface is the usual interface and all of the functionality
of the part is available through this interface. Only a subset of functions are available
through the Address/Address Multiplexed (A/A Mux) Interface.
Follow the section
Firmware hub (FWH) bus operations
below and the section
Address/Address multiplexed (A/A Mux) bus operations
below for a description of the bus
operations on each interface.
3.1
Firmware hub (FWH) bus operations
The Firmware Hub (FWH) Interface consists of four data signals (FWH0-FWH3), one control
line (FWH4) and a clock (CLK). In addition protection against accidental or malicious data
corruption can be achieved using two further signals (TBL and WP). Finally two reset
signals (RP and INIT) are available to put the memory into a known state.
The data signals, control signal and clock are designed to be compatible with PCI electrical
specifications. The interface operates with clock speeds up to 33MHz.
The following operations can be performed using the appropriate bus cycles: Bus Read, Bus
Write, Standby, Reset and Block Protection.
3.1.1
Bus Read
Bus Read operations read from the memory cells, specific registers in the Command
Interface or Firmware Hub Registers. A valid Bus Read operation starts when Input
Communication Frame, FWH4, is Low, V
IL
, as Clock rises and the correct Start cycle is on
FWH0-FWH3. On the following clock cycles the Host will send the Memory ID Select,
Address and other control bits on FWH0-FWH3. The memory responds by outputting Sync
data until the wait-states have elapsed followed by Data0-Data3 and Data4-Data7.
Refer to
Table 4: FWH bus Read field definitions
, and
Figure 6: FWH Bus Read waveforms
,
for a description of the Field definitions for each clock cycle of the transfer. See
Table 20:
FWH interface AC signal timing characteristics
, and
Figure 11: FWH interface AC signal
timing waveforms
, for details on the timings of the signals.
3.1.2
Bus Write
Bus Write operations write to the Command Interface or Firmware Hub Registers. A valid
Bus Write operation starts when Input Communication Frame, FWH4, is Low, V
IL
, as Clock
rises and the correct Start cycle is on FWH0-FWH3. On the following Clock cycles the Host
will send the Memory ID Select, Address, other control bits, Data0-Data3 and Data4-Data7
on FWH0-FWH3. The memory outputs Sync data until the wait-states have elapsed.
Refer to
Table 5: FWH bus Write field definitions
, and
Figure 7: FWH Bus Write waveforms
,
for a description of the Field definitions for each clock cycle of the transfer. See
Table 20:
FWH interface AC signal timing characteristics
, and
Figure 11: FWH interface AC signal
timing waveforms
, for details on the timings of the signals.
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參數(shù)描述 |
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| M50FW080 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory |
| M50FW080K | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory |
| M50FW080K1 | 功能描述:閃存 3.6V 8M (1Mx8) RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M50FW080K1G | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory |
| M50FW080K1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory |
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