參數(shù)資料
型號(hào): M50FW040NB5G
廠商: 意法半導(dǎo)體
英文描述: 4-Mbit (512 Kb x8, uniform block) 3-V supply firmware hub Flash memory
中文描述: 4兆位(512 KB的× 8,均勻塊)3 - V電源供電的閃存固件樞紐
文件頁數(shù): 20/53頁
文件大?。?/td> 278K
代理商: M50FW040NB5G
Bus operations
M50FW040
20/53
Table 4.
Figure 6.
FWH Bus Read waveforms
FWH bus Read field definitions
Clock
Cycle
Number
Clock
Cycle
Count
Field
FWH0-
FWH3
Memory
I/O
Description
1
1
START
1101b
I
On the rising edge of CLK with FWH4 Low, the
contents of FWH0-FWH3 indicate the start of a FWH
Read cycle.
2
1
IDSEL
XXXX
I
Indicates which FWH Flash Memory is selected. The
value on FWH0-FWH3 is compared to the IDSEL
strapping on the FWH Flash Memory pins to select
which FWH Flash Memory is being addressed.
3-9
7
ADDR
XXXX
I
A 28-bit address phase is transferred starting with
the most significant nibble first.
10
1
MSIZE
0000b
I
Always 0000b (only single byte transfers are
supported).
11
1
TAR
1111b
I
The host drives FWH0-FWH3 to 1111b to indicate a
turnaround cycle.
12
1
TAR
1111b
(float)
O
The FWH Flash Memory takes control of FWH0-
FWH3 during this cycle.
13-14
2
WSYN
C
0101b
O
The FWH Flash Memory drives FWH0-FWH3 to
0101b (short wait-sync) for two clock cycles,
indicating that the data is not yet available. Two wait-
states are always included.
15
1
RSYN
C
0000b
O
The FWH Flash Memory drives FWH0-FWH3 to
0000b, indicating that data will be available during
the next clock cycle.
16-17
2
DATA
XXXX
O
Data transfer is two CLK cycles, starting with the
least significant nibble.
18
1
TAR
1111b
O
The FWH Flash Memory drives FWH0-FWH3 to
1111b to indicate a turnaround cycle.
19
1
TAR
1111b
(float)
N/A
The FWH Flash Memory floats its outputs, the host
takes control of FWH0-FWH3.
AI03437
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
START
IDSEL
ADDR
MSIZE
TAR
SYNC
DATA
TAR
1
1
7
1
2
3
2
2
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