參數(shù)資料
型號(hào): M50FW040NB5G
廠商: 意法半導(dǎo)體
英文描述: 4-Mbit (512 Kb x8, uniform block) 3-V supply firmware hub Flash memory
中文描述: 4兆位(512 KB的× 8,均勻塊)3 - V電源供電的閃存固件樞紐
文件頁(yè)數(shù): 12/53頁(yè)
文件大?。?/td> 278K
代理商: M50FW040NB5G
Signal descriptions
M50FW040
12/53
2
Signal descriptions
There are two different bus interfaces available on this part. The active interface is selected
before power-up or during Reset using the Interface Configuration Pin, IC.
The signals for each interface are discussed in the
Firmware hub (FWH) signal descriptions
section and the
Address/Address multiplexed (A/A Mux) signal descriptions
section below.
The supply signals are discussed in the
Supply signal descriptions
section below.
2.1
Firmware hub (FWH) signal descriptions
For the Firmware Hub (FWH) Interface see <Blue>Figure 1., Logic diagram (FWH
interface), and <Blue>Table 1., Signal names (FWH interface).
2.1.1
Input/Output communications (FWH0-FWH3)
All Input and Output Communication with the memory take place on these pins. Addresses
and Data for Bus Read and Bus Write operations are encoded on these pins.
2.1.2
Input communication frame (FWH4)
The Input Communication Frame (FWH4) signals the start of a bus operation. When Input
Communication Frame is Low, V
IL
, on the rising edge of the Clock a new bus operation is
initiated. If Input Communication Frame is Low, V
IL
, during a bus operation then the
operation is aborted. When Input Communication Frame is High, V
IH
, the current bus
operation is proceeding or the bus is idle.
2.1.3
Identification inputs (ID0-ID3)
The Identification Inputs select the address that the memory responds to. Up to 16
memories can be addressed on a bus. For an address bit to be ‘0’ the pin can be left floating
or driven Low, V
IL
; an internal pull-down resistor is included with a value of R
IL
. For an
address bit to be ‘1’ the pin must be driven High, V
IH
; there will be a leakage current of I
LI2
through each pin when pulled to V
IH
; see <Blue>Table 18.
By convention the boot memory must have address ‘0000’ and all additional memories take
sequential addresses starting from ‘0001’.
2.1.4
General-purpose inputs (FGPI0-FGPI4)
The General Purpose Inputs can be used as digital inputs for the CPU to read. The General
Purpose Inputs Register holds the values on these pins. The pins must have stable data
from before the start of the cycle that reads the General Purpose Input Register until after
the cycle is complete. These pins must not be left to float, they should be driven Low, V
IL,
or
High, V
IH
.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M50FW040NB5P 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:4-Mbit (512 Kb x8, uniform block) 3-V supply firmware hub Flash memory
M50FW040NB5TG 功能描述:閃存 SERIAL FLASH RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線(xiàn)寬度:1 bit 存儲(chǔ)類(lèi)型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類(lèi)型: 接口類(lèi)型:SPI 訪(fǎng)問(wèn)時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
M50FW040NB5TP 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:4-Mbit (512 Kb x8, uniform block) 3-V supply firmware hub Flash memory
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