參數(shù)資料
型號(hào): M50FLW080AN5T
廠商: STMICROELECTRONICS
元件分類: PROM
英文描述: 1M X 8 FLASH 3V PROM, 11 ns, PDSO40
封裝: 10 X 20 MM, PLASTIC, TSOP-40
文件頁數(shù): 8/53頁
文件大小: 945K
代理商: M50FLW080AN5T
M50FLW080A, M50FLW080B
16/53
Table 8. LPC Bus Read Field Definitions (1-Byte)
Figure 9. LPC Bus Read Waveforms (1-Byte)
Clock Cycle
Number
Clock
Cycle
Count
Field
LAD0-
LAD3
Memory
I/O
Description
1
START
0000b
I
On the rising edge of CLK with LFRAME Low, the contents
of LAD0-LAD3 must be 0000b to indicate the start of a
LPC cycle.
21
CYCTYPE
+ DIR
0100b
I
Indicates the type of cycle and selects 1-byte reading. Bits
3:2 must be 01b. Bit 1 indicates the direction of transfer: 0b
for read. Bit 0 is Don’t Care.
3-10
8
ADDR
XXXX
I
A 32-bit address is transferred, with the most significant
nibble first. A23-A31 must be set to 1. A22=1 for memory
access, and A22=0 for register access. Table 5. shows the
appropriate values for A21-A20.
11
1
TAR
1111b
I
The host drives LAD0-LAD3 to 1111b to indicate a
turnaround cycle.
12
1
TAR
1111b
(float)
O
The LPC Flash Memory takes control of LAD0-LAD3
during this cycle.
13-14
2
WSYNC
0101b
O
The LPC Flash Memory drives LAD0-LAD3 to 0101b
(short wait-sync) for two clock cycles, indicating that the
data is not yet available. Two wait-states are always
included.
15
1
RSYNC
0000b
O
The LPC Flash Memory drives LAD0-LAD3 to 0000b,
indicating that data will be available during the next clock
cycle.
16-17
2
DATA
XXXX
O
Data transfer is two CLK cycles, starting with the least
significant nibble.
18
1
TAR
1111b
O
The LPC Flash Memory drives LAD0-LAD3 to 1111b to
indicate a turnaround cycle.
19
1
TAR
1111b
(float)
N/A
The LPC Flash Memory floats its outputs, the host takes
control of LAD0-LAD3.
AI04429
CLK
LFRAME
LAD0-LAD3
Number of
clock cycles
START
CYCTYPE
+ DIR
ADDR
TAR
SYNC
DATA
TAR
1182322
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