參數(shù)資料
型號: M50FLW080AN5T
廠商: STMICROELECTRONICS
元件分類: PROM
英文描述: 1M X 8 FLASH 3V PROM, 11 ns, PDSO40
封裝: 10 X 20 MM, PLASTIC, TSOP-40
文件頁數(shù): 6/53頁
文件大?。?/td> 945K
代理商: M50FLW080AN5T
M50FLW080A, M50FLW080B
14/53
Table 6. FWH Bus Read Field Definitions
Figure 7. FWH Bus Read Waveforms
Clock
Cycle
Number
Clock
Cycle
Count
Field
FWH0-
FWH3
Memory
I/O
Description
1
START
1101b
I
On the rising edge of CLK with FWH4 Low, the contents of FWH0-
FWH3 indicate the start of a FWH Read cycle.
21
IDSEL
XXXX
I
Indicates which FWH Flash Memory is selected. The value on
FWH0-FWH3 is compared to the IDSEL strapping on the FWH
Flash Memory pins to select which FWH Flash Memory is being
addressed.
3-9
7
ADDR
XXXX
I
A 28-bit address is transferred, with the most significant nibble
first. For the multi-byte read operation, the least significant bits
(MSIZE of them) are treated as Don't Care, and the read operation
is started with each of these bits reset to 0. Address lines A20-21
and A23-27 are treated as Don’t Care during a normal memory
array access, with A22=1, but are taken into account for a register
access, with A22=0. (See Table 15.)
10
1
MSIZE
XXXX
I
This one clock cycle is driven by the host to determine the number
of Bytes that will be transferred. M50FLW080 supports: single
Byte transfer (0000b), 2-Byte transfer (0001b), 4-Byte transfer
(0010b), 16-Byte transfer (0100b) and 128-Byte transfer (0111b).
11
1
TAR
1111b
I
The host drives FWH0-FWH3 to 1111b to indicate a turnaround
cycle.
12
1
TAR
1111b
(float)
O
The FWH Flash Memory takes control of FWH0-FWH3 during this
cycle.
13-14
2
WSYNC
0101b
O
The FWH Flash Memory drives FWH0-FWH3 to 0101b (short
wait-sync) for two clock cycles, indicating that the data is not yet
available. Two wait-states are always included.
15
1
RSYNC
0000b
O
The FWH Flash Memory drives FWH0-FWH3 to 0000b, indicating
that data will be available during the next clock cycle.
16-17M=2nDATA
XXXX
O
Data transfer is two CLK cycles, starting with the least significant
nibble. If multi-Byte read operation is enabled, repeat cycle-16 and
cycle-17
n times, where n = 2MSIZE.
previous
+1
1
TAR
1111b
O
The FWH Flash Memory drives FWH0-FWH3 to 1111b to indicate
a turnaround cycle.
previous
+1
1TAR
1111b
(float)
N/A
The FWH Flash Memory floats its outputs, the host takes control
of FWH0-FWH3.
AI08433B
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
START
IDSEL
ADDR
MSIZE
TAR
SYNC
DATA
TAR
117123
M
2
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