參數(shù)資料
型號: M50FLW040AK5TG
廠商: 意法半導體
英文描述: 4-Mbit (5 】 64 Kbyte blocks + 3 】 16 】 4 Kbyte sectors) 3-V supply Firmware Hub / low-pin count Flash memory
中文描述: 4兆位(5】64字節(jié)塊3】16】4 Kbyte的)3 - V電源供電固件集線器/低引腳數(shù)的閃存
文件頁數(shù): 46/64頁
文件大?。?/td> 338K
代理商: M50FLW040AK5TG
DC and AC parameters
M50FLW040A, M50FLW040B
46/64
Figure 16.
A/A Mux interface Read AC waveforms
A/A Mux interface Read AC characteristics
AI03406
tAVAV
tCLAX
tCHAX
tGLQX
tGLQV
tGHQX
VALID
A0-A10
G
DQ0-DQ7
RC
tCHQV
tGHQZ
COLUMN ADDR VALID
W
RP
tPHAV
ROW ADDR VALID
NEXT ADDR VALID
tAVCL
tAVCH
Table 28.
Symbol
Parameter
Test Condition
Value
Unit
t
AVAV
Read Cycle Time
Min
250
ns
t
AVCL
Row Address Valid to RC Low
Min
50
ns
t
CLAX
RC Low to Row Address Transition
Min
50
ns
t
AVCH
Column Address Valid to RC high
Min
50
ns
t
CHAX
t
CHQV(1)
t
GLQV(1)
RC High to Column Address Transition
Min
50
ns
RC High to Output Valid
Max
150
ns
Output Enable Low to Output Valid
Max
50
ns
t
PHAV
RP High to Row Address Valid
Min
1
μ
s
t
GLQX
Output Enable Low to Output Transition
Min
0
ns
t
GHQZ
Output Enable High to Output Hi-Z
Max
50
ns
t
GHQX
Output Hold from Output Enable High
Min
0
ns
1.
G may be delayed up to t
CHQV
– t
GLQV
after the rising edge of RC without impact on t
CHQV
.
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