參數(shù)資料
型號(hào)： M50FLW040AK5TG
廠商： 意法半導(dǎo)體
英文描述： 4-Mbit (5 】 64 Kbyte blocks + 3 】 16 】 4 Kbyte sectors) 3-V supply Firmware Hub / low-pin count Flash memory
中文描述： 4兆位（5】64字節(jié)塊3】16】4 Kbyte的）3 - V電源供電固件集線器/低引腳數(shù)的閃存
文件頁(yè)數(shù)： 14/64頁(yè)
文件大?。?/td> 338K
代理商： M50FLW040AK5TG
Signal descriptions
M50FLW040A, M50FLW040B
14/64
2.1.4
General-purpose inputs (GPI0-GPI4)
The General Purpose Inputs can be used as digital inputs for the CPU to read, with their
contents being available in the General Purpose Inputs Register. The pins must have stable
data throughout the entire cycle that reads the General Purpose Input Register. These pins
should be driven Low, V
IL,
or High, V
IH
, and must not be left floating.
2.1.5
Interface Configuration (IC)
The Interface Configuration input selects whether the FWH/LPC interface or the
Address/Address Multiplexed (A/A Mux) Interface is used. The state of the Interface
Configuration, IC, should not be changed during operation of the memory device, except for
selecting the desired interface in the period before power-up or during a Reset.
To select the FWH/LPC Interface, the Interface Configuration pin should be left to float or
driven Low, V
IL
. To select the Address/Address Multiplexed (A/A Mux) Interface, the pin
should be driven High, V
IH
. An internal pull-down resistor is included with a value of R
IL
;
there will be a leakage current of I
LI2
through each pin when pulled to V
IH
.
2.1.6
Interface Reset (RP)
The Interface Reset (RP) input is used to reset the device. When Interface Reset (RP) is
driven Low, V
IL
, the memory is in Reset mode (the outputs go to high impedance, and the
current consumption is minimized). When RP is driven High, V
IH
, the device is in normal
operation. After exiting Reset mode, the memory enters Read mode.
2.1.7
CPU Reset (INIT)
The CPU Reset, INIT, signal is used to Reset the device when the CPU is reset. It behaves
identically to Interface Reset, RP, and the internal Reset line is the logical OR (electrical
AND) of RP and INIT.
2.1.8
Clock (CLK)
The Clock, CLK, input is used to clock the signals in and out of the Input/Output
Communication Pins, FWH0/LAD0-FWH3/LAD3. The Clock conforms to the PCI
specification.
2.1.9
Top Block Lock (TBL)
The Top Block Lock input is used to prevent the Top Block (Block 7) from being changed.
When Top Block Lock, TBL, is driven Low, V
IL
, program and erase operations in the Top
Block have no effect, regardless of the state of the Lock Register. When Top Block Lock,
TBL, is driven High, V
IH
, the protection of the Block is determined by the Lock Register. The
state of Top Block Lock, TBL, does not affect the protection of the Main Blocks (Blocks 0 to
6). For details, see
Appendix A
.
Top Block Lock, TBL, must be set prior to a program or erase operation being initiated, and
must not be changed until the operation has completed, otherwise unpredictable results
may occur. Similarly, unpredictable behavior is possible if WP is changed during Program or
Erase Suspend, and care should be taken to avoid this.
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M50FLW040AK5TP 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4-Mbit (5 】 64 Kbyte blocks + 3 】 16 】 4 Kbyte sectors) 3-V supply Firmware Hub / low-pin count Flash memory
M50FLW040AN1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory
M50FLW040AN1G 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory
M50FLW040AN1P 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory
M50FLW040AN1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory
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