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參數(shù)資料
| 型號： | M48T559YMH1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO28 |
| 封裝： | 0.330 INCH, PLASTIC, SOH-28 |
| 文件頁數(shù)： | 26/26頁 |
| 文件大小： | 364K |
| 代理商： | M48T559YMH1 |
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M48T559Y
Data Retention Mode
Should the supply voltage decay, the RAM will au-
tomatically power-fail deselect, write protecting it-
self when VCC falls within the VPFD (max), VPFD
(min) window. All outputs become high imped-
ance, and all inputs are treated as “Don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's con-
tent. At voltages below VPFD (min), the user can be
assured the memory will be in a write protected
state, provided the VCC fall time is not less than tF.
The M48T559Y may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. There-
fore, decoupling of the power supply lines is rec-
ommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48T559Y for
an accumulated period of at least 7 years when
VCC is less than VSO. As system power returns
and VCC rises above VSO, the battery is discon-
nected, and the power supply is switched to exter-
nal VCC. Write protection continues until VCC
reaches VPFD (max) plus trec.
For more information on Battery Storage Life refer
to the Application Note AN1012.
CLOCK OPERATION
Reading the Clock
Updates to the TIMEKEEPER registers should
be halted before clock data is read to prevent
reading data in transition. Because the BiPORT
TIMEKEEPER cells in the RAM array are only
data registers and not the actual clock counters,
so updating the registers can be halted without
disturbing the clock itself.
Updating is halted when a '1' is written to the
READ Bit, D6 in the Control register (1FF8h). As
long as a '1' remains in that position, updating is
halted.
After a halt is issued, the registers reflect the
count; that is, the day, date, and the time that were
current at the moment the halt command was is-
sued.
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a '0.'
Setting the Clock
Bit D7 of the Control register (1FF8h) is the
WRITE Bit. Setting the WRITE Bit to a '1,' like the
READ Bit, halts updates to the TIMEKEEPER reg-
isters. The user can then load them with the cor-
rect day, date, and time data in 24 hour BCD
format (see Table 4., page 10). Resetting the
WRITE Bit to a '0' then transfers the values of all
time registers (1FF9h-1FFFh) to the actual TIME-
KEEPER counters and allows normal operation to
resume. After the WRITE Bit is reset, the next
clock update will occur in one second.
See the Application Note AN923, “TIMEKEEPER
rolling into the 21st Century” for information on
Century Rollover.
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit is the MSB of the seconds register. Setting it to
a '1' stops the oscillator. The M48T559Y is
shipped from STMicroelectronics with the STOP
Bit set to a '1.' When reset to a '0,' the M48T559Y
oscillator starts within one second.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M48T559Y-MH1 | 功能描述:RAM其它 8KX8 TIMEKEEPR RoHS:否 制造商:Freescale Semiconductor 封裝:Tray |
| M48T559YMH1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Kbit 8Kb x8 TIMEKEEPER SRAM with ADDRESS/DATA MULTIPLEXED |
| M48T559YSH | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Kbit 8Kb x8 TIMEKEEPER SRAM with ADDRESS/DATA MULTIPLEXED |
| M48T58 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0V, 64 Kbit (8 Kb x 8) TIMEKEEPER SRAM |
| M48T58_07 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0V, 64 Kbit (8 Kb x 8) TIMEKEEPER SRAM |
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