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參數(shù)資料
| 型號： | M48T559YMH1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO28 |
| 封裝： | 0.330 INCH, PLASTIC, SOH-28 |
| 文件頁數(shù)： | 24/26頁 |
| 文件大?。?/td> | 364K |
| 代理商： | M48T559YMH1 |
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M48T559Y
RAM OPERATION
Four control signals, AS0, AS1, R and W, are used
to access the M48T559Y. The address latches are
loaded from the address/address/data bus in re-
sponse to rising edge signals applied to the Ad-
dress Strobe 0 (AS0) and Address Strobe 1 (AS1)
signals. AS0 is used to latch the lower 8 bits of ad-
dress, and AS1 is used to latch the upper 5 bits of
address.
It is not however necessary to follow any particular
order. The inputs are in parallel for the two ad-
dress bytes (upper and lower) and can be latched
in any order as long as the correct strobe is used.
It is necessary to meet the set-up and hold times
given in the AC specifications with valid address
information in order to properly latch the address.
If the upper and/or lower order addresses are cor-
rect from a prior cycle, it is not necessary to repeat
the address latching sequence.
A WRITE operation requires valid data to be
placed on the bus (AD0-AD7), followed by the ac-
tivation of the WRITE Enable (W) line. Data on the
bus will be written to the RAM, provided that the
WRITE timing specifications are met. During a
READ cycle, the READ Enable (R) signal is driven
active. Data from the RAM will become valid on
the bus provided that the RAM READ access tim-
ing specifications are met.
The W and R signals should never be active at the
same time. In addition, E must be active before
any control line is recognized (except for AD0-AD7
and AS0, AS1).
Figure 5. READ Mode AC Waveforms
Note: AD5-AD7 are “Don't care” when latching upper address.
AI01671B
AS0
R
AD0-AD7
E
tASLASH
tELRL
AS1
tAS
tAH
LOW ADDRESS VALID
tAS
tAH
UPPER ADDRESS VALID
tRHDZ
tRLDV
DATA OUT
VALID
tEHDZ
tRLRH
tASHRL
tASLASH
tELEH
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PDF描述 |
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| M48T58-70PC1 | 0 TIMER(S), REAL TIME CLOCK, PDIP28 |
| M48T58Y-70MH1E | 0 TIMER(S), REAL TIME CLOCK, PDSO28 |
| M48T58Y-70PC1TR | 0 TIMER(S), REAL TIME CLOCK, PDIP28 |
| M48T59V-70MH1E | 0 TIMER(S), REAL TIME CLOCK, PDSO28 |
| M48T59V-70PC1 | 0 TIMER(S), REAL TIME CLOCK, PDIP28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M48T559Y-MH1 | 功能描述:RAM其它 8KX8 TIMEKEEPR RoHS:否 制造商:Freescale Semiconductor 封裝:Tray |
| M48T559YMH1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Kbit 8Kb x8 TIMEKEEPER SRAM with ADDRESS/DATA MULTIPLEXED |
| M48T559YSH | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Kbit 8Kb x8 TIMEKEEPER SRAM with ADDRESS/DATA MULTIPLEXED |
| M48T58 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0V, 64 Kbit (8 Kb x 8) TIMEKEEPER SRAM |
| M48T58_07 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0V, 64 Kbit (8 Kb x 8) TIMEKEEPER SRAM |
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