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參數(shù)資料
| 型號(hào)： | M44C890 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low-Current Microcontroller for Wireless Communication |
| 中文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SSO-20 |
| 文件頁數(shù)： | 44/63頁 |
| 文件大?。?/td> | 503K |
| 代理商： | M44C890 |
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M44C890
M44C090
Rev.A4, 14-Dec-01
44 (63)
Due to the byte-orientated data control, the SSI when
running normally generates serial bit streams which are
submultiples of 8 bits. An SSI output masking (OMSK)
function permits, however, the generation of bit streams
of any length. The OMSK signal is derived indirectly
from the 4-bit prescaler of the Timer 2 and masks out a
programmable number of unrequired trailing data bits
during the shifting out of the final data word in the bit
stream. The number of non-masked data bits is defined by
the value pre-programmed in the prescaler compare
register. To use output masking, the modulator stop mode
bit (MSM) must be set to
’
0
’
before programming the
final data word into the SSI transmit buffer. This in turn,
enables shift clocks to the prescaler when this final word
is shifted out. On reaching the compare value, the
prescaler triggers the OMSK signal and all following data
bits are blanked.
Internal 2-Wire Multi-Chip Link
Two additional on-chip pads (MCL_SC and MCL_SD)
for the SC and the SD line can be used as chip-to-chip link
for multi-chip applications. These pads can be activated
by setting the MCL-bit in the SISC-register.
SCL
SDA
MCL_SC
MCL_SD
U505M
M44C090
V
DD
BP40/SC
BP43/SD
Multi chip link
13835
V
SS
Figure 51. Multi-chip link
13834
8-bit shift register
MSB
LSB
Shift_CL
SO
Control
SI
Timer 2
Output
SSI-control
SO
Compare 2/1
4-bit counter 2/1
CL2/1
SCL
CM1
OMSK
SC
TOG2
POUT
T1OUT
SYSCL
/2
Figure 52. SSI output masking function
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