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參數(shù)資料
| 型號(hào)： | M44C890 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low-Current Microcontroller for Wireless Communication |
| 中文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SSO-20 |
| 文件頁數(shù)： | 40/63頁 |
| 文件大小： | 503K |
| 代理商： | M44C890 |
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M44C890
M44C090
Rev.A4, 14-Dec-01
40 (63)
The SSI then continues shifting in the following 8-bit
telegram. If, during this time the first telegram has been
read by the controller, the second telegram will also be
transferred in the same way into the receive buffer and the
SSI will continue clocking in the next telegram. Should,
however, the first telegram not have been read
(SRDY=1), then the SSI will stop, temporarily holding
the second telegram in the shift register until a certain
point of time when the controller is able to service the
receive buffer. In this way no data is lost or overwritten.
Deactivating the SSI (SIR=1) in mid
–
telegram will
immediately stop the shift clock and latch the present
contents of the shift register into the receive buffer. This
can be used for clocking in a data telegram of less than 8
bits in length. Care should be taken to read out the final
complete 8-bit data telegram of a multiple word message
before deactivating the SSI (SIR=1) and terminating the
reception. After termination, the shift register contents
will overwrite the receive buffer.
7 6 5 4 3 2 1
0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1
0
msb
lsb
tx data 1
tx data 2
tx data 3
msb
lsb msb
lsb
Write STB
(tx data 2)
Write STB
(tx data 3)
Write STB
(tx data 1)
SC
SD
SIR
SRDY
Interrupt
(IFN = 0)
Interrupt
(IFN = 1)
ACT
13824
Figure 45. Example of 8-bit synchronous transmit operation
4 3 2 1 0
7 6 5 4 3 2 1 0
msb
lsb
rx data 1
rx data 2
rx data 3
msb
lsb
msb
lsb
Read SRB
(rx data 2)
Read SRB
(rx data 3)
Read SRB
(rx data 1)
SC
SD
SIR
SRDY
Interrupt
(IFN = 0)
Interrupt
(IFN = 1)
ACT
13825
7 6 5
4 3 2 1 0
7 6 5
7 6 5 4
Figure 46. Example of 8-bit synchronous receive operation
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