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參數(shù)資料
| 型號(hào)： | M41T60Q6F |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取 |
| 英文描述： | 1 TIMER(S), REAL TIME CLOCK, QCC16 |
| 封裝： | 3 X 3 MM, LEAD FREE, QFN-16 |
| 文件頁數(shù)： | 3/27頁 |
| 文件大?。?/td> | 534K |
| 代理商： | M41T60Q6F |
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M41T60
Operation
Doc ID 10396 Rev 12
2.3
WRITE mode
In this mode the master transmitter transmits to the M41T60 slave receiver. Bus protocol is
shown in
Figure 10 on page 11. Following the START condition and slave address, a logic '0'
(R/W = 0) is placed on the bus and indicates to the addressed device that word address An
will follow and is to be written to the on-chip address pointer. The data word to be written to
the memory is strobed in next and the internal address pointer is increased to the next
address location on the reception of an acknowledge clock. The M41T60 slave receiver will
send an acknowledge clock to the master transmitter after it has received the slave address
and again after it has received the word address and each data byte.
Figure 10. WRITE mode sequence
AI00591
BUS ACTIVITY:
AC
K
S
AC
K
AC
K
AC
K
AC
K
ST
OP
ST
AR
T
P
SDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n
DATA n+1
DATA n+X
WORD
ADDRESS (An)
SLAVE
ADDRESS
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