參數(shù)資料
型號(hào)： M41T60Q6F
廠商： STMICROELECTRONICS
元件分類： 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述： 1 TIMER(S), REAL TIME CLOCK, QCC16
封裝： 3 X 3 MM, LEAD FREE, QFN-16
文件頁(yè)數(shù)： 27/27頁(yè)
文件大?。?/td> 534K
代理商： M41T60Q6F
M41T60
Operation
Doc ID 10396 Rev 12
Figure 6.
Acknowledgement sequence
2.2
READ mode
In this mode, the master reads the M41T60 slave after setting the slave address
(see
Figure 7). Following the WRITE mode control bit (R/W = 0) and the acknowledge bit,
the word address An is written to the on-chip address pointer. Next the START condition and
slave address are repeated, followed by the READ mode control bit (R/W = 1). At this point,
the master transmitter becomes the master receiver. The data byte which was addressed
will be transmitted and the master receiver will send an acknowledge bit to the slave
transmitter. The address pointer is only increased on reception of an acknowledge bit. The
M41T60 slave transmitter will now place the data byte at address An+1 on the bus. The
master receiver reads and acknowledges the new byte and the address pointer is increased
to An+2.
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (0h to 6h). The update will resume due to a stop condition or when the
pointer increments to any non-clock address (7h).
An alternate READ mode may also be implemented, whereby the master reads the M41T60
slave without first writing to the (volatile) address pointer. The first address that is read is the
last one stored in the pointer (see
Figure 7.
Slave address location
AI00601
DATA OUTPUT
BY RECEIVER
DATA OUTPUT
BY TRANSMITTER
SCL FROM
MASTER
START
CLOCK PULSE FOR
ACKNOWLEDGEMENT
12
8
9
MSBLSB
AI00602
R/W
SLAVE ADDRESS
START
A
01
0
11
M
S
B
L
S
B
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