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參數(shù)資料
| 型號： | M41T256YMT7TR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO44 |
| 封裝： | 0.330 INCH, PLASTIC, SOIC-44 |
| 文件頁數(shù)： | 26/27頁 |
| 文件大小： | 523K |
| 代理商： | M41T256YMT7TR |
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M41T256Y
8/27
Figure 9. Bus Timing Requirements Sequence
Table 2. AC Characteristics
Note: 1. Valid for Ambient Operating Temperature: TA = –25 to 70°C; VCC = 4.5 to 5.5V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
Symbol
Parameter(1)
Min
Max
Unit
fSCL
SCL Clock Frequency
0
400
kHz
tBUF
Time the bus must be free before a new transmission can start
1.3
s
tF
SDA and SCL Fall Time
300
ns
tHD:DAT
Data Hold Time
0
s
tHD:STA
START Condition Hold Time
(after this period the first clock pulse is generated)
600
ns
tHIGH
Clock High Period
600
ns
tLOW
Clock Low Period
1.3
s
tR
SDA and SCL Rise Time
300
ns
tSU:DAT
(2)
Data Setup Time
100
ns
tSU:STA
START Condition Setup Time
(only relevant for a repeated start condition)
600
ns
tSU:STO
STOP Condition Setup Time
600
ns
AI00589
SDA
P
tSU:STO
tSU:STA
tHD:STA
SR
SCL
tSU:DAT
tF
tHD:DAT
tR
tHIGH
tLOW
tHD:STA
tBUF
S
P
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