參數(shù)資料
型號(hào)： M41T256YMT7F
廠商： STMICROELECTRONICS
元件分類： 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述： REAL TIME CLOCK, PDSO44
封裝： 0.330 INCH, LEAD FREE, PLASTIC, SOIC-44
文件頁(yè)數(shù)： 4/30頁(yè)
文件大?。?/td> 353K
代理商： M41T256YMT7F
Product(s)
- Obsolete
Product(s)
Product(s)
- Obsolete
Product(s)
Operating modes
M41T256Y
Figure 6.
Bus timing requirements sequence
Table 2.
AC characteristics
2.2
Read mode
In this mode the master reads the M41T256Y slave after setting the slave address (see
Figure 7 on page 13). Following the WRITE mode control bit (R/W=0) and the Acknowledge
Bit, the byte addresses A(0) and A(1) are written to the on-chip address pointer (MSB of
address byte A(0) is a “Don’t care”). Next the START condition and slave address are
repeated followed by the READ mode control bit (R/W=1). At this point the master
transmitter becomes the master receiver. The data byte which was addressed will be
transmitted and the master receiver will send an acknowledge bit to the slave transmitter.
The address pointer is only incremented on reception of an acknowledge clock. The
M41T256Y slave transmitter will now place the data byte at address An+1 on the bus, the
Symbol
Parameter(1)
1.
Valid for ambient operating temperature: TA = –25 to 70°C; VCC = 4.5 to 5.5V (except where noted).
Min
Max
Unit
fSCL
SCL clock frequency
0
400
kHz
tBUF
Time the bus must be free before a new transmission can
start
1.3
s
tF
SDA and SCL fall time
300
ns
tHD:DAT
Data hold time
0
s
tHD:STA
START condition hold time
(after this period the first clock pulse is generated)
600
ns
tHIGH
Clock high period
600
ns
tLOW
Clock low period
1.3
s
tR
SDA and SCL rise time
300
ns
tSU:DAT
(2)
2.
Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL
Data setup time
100
ns
tSU:STA
START condition setup time
(only relevant for a repeated start condition)
600
ns
tSU:STO
STOP condition setup time
600
ns
AI00589
SDA
P
tSU:STO
tSU:STA
tHD:STA
SR
SCL
tSU:DAT
tF
tHD:DAT
tR
tHIGH
tLOW
tHD:STA
tBUF
S
P
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