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參數(shù)資料
| 型號： | M41T256YMT7F |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復及定時提取 |
| 英文描述： | REAL TIME CLOCK, PDSO44 |
| 封裝： | 0.330 INCH, LEAD FREE, PLASTIC, SOIC-44 |
| 文件頁數(shù)： | 30/30頁 |
| 文件大?。?/td> | 353K |
| 代理商： | M41T256YMT7F |
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M41T256Y
Operating modes
2
Operating modes
The M41T256Y clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 256K bytes
contained in the device can then be accessed sequentially in the following order:
0-7FEF = General purpose RAM
7FF0-7FF6 = Reserved
7FF7h = Tenths/hundredths register
7FF8h = Control register
7FF9h = Seconds register
7FFAh = Minutes register
7FFBh = Hour register
7FFCh = Tamper/day register
7FFDh = Date register
7FFEh = Month register
7FFFh = Year register
The M41T256Y clock continually monitors VCC for an out-of tolerance condition. Should
VCC fall below VPFD, the device terminates an access in progress and resets the device
address counter. Inputs to the device will not be recognized at this time to prevent
erroneous data from being written to the device from an out-of-tolerance system. When VCC
falls below VSO, the device automatically switches over to the battery and powers down into
an ultra low current mode of operation to conserve battery life. As system power returns and
VCC rises above VSO, the battery is disconnected, and the power supply is switched to
external VCC. Write protection continues until VCC reaches VPFD plus tREC.
For more information on Battery Storage Life refer to Application Note AN1012.
2.1
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a
bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must
be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
●
Data transfer may be initiated only when the bus is not busy.
●
During data transfer, the data line must remain stable whenever the clock line is high.
●
Changes in the data line, while the clock line is high, will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
2.1.1
Bus not busy
Both data and clock lines remain High.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M41T256YMT7TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit 32K x8 SERIAL RTC |
| M41T256YSH | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit 32K x8 SERIAL RTC |
| M41T315V | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Serial access phantom RTC supervisor |
| M41T315V/W | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Serial Access Phantom RTC Supervisor |
| M41T315V-65MH6E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Serial Access Phantom RTC Supervisor |
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