參數(shù)資料
型號(hào): M41ST95W
廠商: 意法半導(dǎo)體
英文描述: 5.0 or 3.0V, 512 bit (64 bit x8) Serial RTC (SPI) SRAM and NVRAM Supervisor(5.0/3.0V, 512位(64位x8)串行RTC(SPI) SRAM和NVRAM監(jiān)控電路)
中文描述: 5.0或3.0V,512位(64位× 8)串行時(shí)鐘(SPI)的靜態(tài)存儲(chǔ)器和NVRAM主管(5.0/3.0V,512位(64位× 8)串行時(shí)鐘(SPI)的靜態(tài)存儲(chǔ)器和NVRAM中監(jiān)控電路)
文件頁數(shù): 22/35頁
文件大?。?/td> 602K
代理商: M41ST95W
M41ST95Y*, M41ST95W
22/35
Power-fail INPUT/OUTPUT
The Power-Fail Input (PFI) is compared to an in-
ternal reference voltage (1.25V). If PFI is less than
the power-fail threshold (V
PFI
), the Power-Fail
Output (PFO) will go low. This function is intended
for use as an under-voltage detector to signal a
failing power supply. Typically PFI is connected
through an external voltage divider (see Figure
17
)
to either the unregulated DC input (if it is available)
or the regulated output of the V
CC
regulator. The
voltage divider can be set up such that the voltage
at PFI falls below V
PFI
several milliseconds before
the regulated V
CC
input to the M41ST95Y/W or the
microprocessor drops below the minimum operat-
ing voltage.
During battery back-up, the power-fail comparator
turns off and PFO goes (or remains) low. This oc-
curs after V
CC
drops below V
PFD
(min). When pow-
er returns, PFO is forced high, irrespective of V
PFI
for the write protect time (t
REC
), which is the time
from V
PFD
(max) until the inputs are recognized. At
the end of this time, the power-fail comparator is
enabled and PFO follows PFI. If the comparator is
unused, PFI should be connected to V
SS
and PFO
left unconnected.
Figure 17. Power-Fail Comparator Hookup
Note: 1. Available only in 28-pin, 300mil SOIC (MX) package.
AI06373
V
CC
V
OUT
V
CC
PFO
SDI
SCL
M41ST95Y/W
WDI
RSTIN2
RSTIN1
PFI
V
SS
V
BAT
IRQ/FT/OUT
SQW
RST
SDO
Unregulated
Voltage
Regulator
V
CC
V
IN
E
EX
E
CON
Pushbutton
Reset
F
To RST
To LED Display
To NMI
To INT
F
32k
(1)
R1
R2
V
CC
E
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參數(shù)描述
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