參數(shù)資料
型號(hào): M41ST95W
廠商: 意法半導(dǎo)體
英文描述: 5.0 or 3.0V, 512 bit (64 bit x8) Serial RTC (SPI) SRAM and NVRAM Supervisor(5.0/3.0V, 512位(64位x8)串行RTC(SPI) SRAM和NVRAM監(jiān)控電路)
中文描述: 5.0或3.0V,512位(64位× 8)串行時(shí)鐘(SPI)的靜態(tài)存儲(chǔ)器和NVRAM主管(5.0/3.0V,512位(64位× 8)串行時(shí)鐘(SPI)的靜態(tài)存儲(chǔ)器和NVRAM中監(jiān)控電路)
文件頁(yè)數(shù): 21/35頁(yè)
文件大?。?/td> 602K
代理商: M41ST95W
21/35
M41ST95Y*, M41ST95W
Power-on Reset
The M41ST95Y/W continuously monitors V
CC
.
When V
CC
falls to the power fail detect trip point,
the RST pulls low (open drain) and remains low on
power-up for t
REC
after V
CC
passes V
PFD
(max).
The RST pin is an open drain output and an appro-
priate pull-up resistor should be chosen to control
rise time.
Reset Input (RSTIN1 and RSTIN2)
The M41ST95Y/W provides two independent in-
puts which can generate an output reset. The du-
ration and function of these resets is identical to a
reset generated by a power cycle. Table
7
and Fig-
ure
16
illustrate the AC reset characteristics of this
function. Pulses shorter than t
RLRH1
and t
RLRH2
will not generate a reset condition. RSTIN1
and
RSTIN2 are each internally pulled up to V
CC
through a 100k
resistor.
Figure 16. RSTIN1 and RSTIN2 Timing Waveforms
Note: 1. Open Drain Output
Table 7. Reset AC Characteristics
Note: 1. Valid for Ambient Operating Temperature: T
A
= –40 to 85°C; V
CC
= 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
2. Pulse width less than 50ns will result in no RESET (for noise immunity).
3. Pulse width less than 20ms will result in no RESET (for noise immunity).
4. Programmable (see
Table 8., page 23
)
5. After crystal oscillator has started
Symbol
Parameter
(1)
Min
Max
Unit
t
RLRH1(2)
RSTIN1 Low to RSTIN1 High
200
ns
t
RLRH2(3)
RSTIN2 Low to RSTIN2 High
100
ms
t
R1HRH(4)
RSTIN1 High to RST High
96
98
ms
t
R2HRH(4,5)
RSTIN2 High to RST High
96
98
ms
AI03665
RSTIN2
RST
(1)
RSTIN1
tRLRH1
tRLRH2
tR1HRH
tR2HRH
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