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參數資料
| 型號： | M41ST87WMX6 |
| 廠商： | 意法半導體 |
| 英文描述： | RECTIFIER SCHOTTKY SINGLE 10A 25V 200A-Ifsm 0.45Vf 1A-IR D2PAK 50/TUBE |
| 中文描述： | 5.0，3.3，或3.0V，1280位（160 × 8）安全串行時鐘和NVRAM篡改檢測與監(jiān)控 |
| 文件頁數： | 17/40頁 |
| 文件大?。?/td> | 610K |
| 代理商： | M41ST87WMX6 |
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17/40
M41ST87Y, M41ST87W
Tamper Current Hi/Tamper Current Lo (TCHI/
TCLO1 and TCHI/TCLO2).
This bit selects the
strength of the internal pull-up or pull-down used
during the sampling of the Normally Closed condi-
tion. The state of the TCHI/TCLO
X
Bit is a “Don’t
care” for Normally Open (TCM
X
= '1') mode (see
Figure 18., page 18
).
RAM Clear (CLR1 and CLR2).
When either of
these bits and the TEB
X
Bit are set to a logic '1,'
the internal 128 bytes of user RAM (see
Figure
15., page 16
) will be cleared to all zeros in the
event of a tamper condition. The 128 bytes of user
RAM will be deselected (invalid data will be read)
until the corresponding TEB
X
Bit is reset to '0.'
RAM Clear External (CLR1
EXT
and CLR2
EXT
).
When either of these bits are set to a logic '1' and
the TEB
X
Bit is also set to logic '1,' the external
SRAM will be cleared and the RST output enabled
(see
Figure
15., page 16
20., page 20
).
Note:
The reset output resulting from a tamper
event will be the same as a reset resulting from a
power-down condition, a watchdog time-out, or a
manual reset (RSTIN1 or RSTIN2).
This is accomplished by forcing TP
CLR
high, which
if used to control the inhibit pin of the DC regulator
(see
Figure 20., page 20
) will also switch off V
OUT
,
depriving the external SRAM of power to the V
CC
pin. V
OUT
will automatically be disconnected from
the battery if the tamper occurs during battery
back-up (see
Figure 19., page 19
). By inhibiting
the DC regulator, the user will also prevent other
and
Figure
inputs from sourcing current to the external SRAM,
allowing it to retain data.
The user may optionally connect an inverting
charge pump to the V
CC
pin of the external SRAM
(see
Figure 20., page 20
). Depending on the pro-
cess technology used for the manufacturing of the
external SRAM, clearing the memory may require
varying durations of negative potential on the V
CC
pin. This device configuration will allow the user to
program the time needed for their particular appli-
cation. Control Bits CLRPW0 and CLRPW1 deter-
mine the duration TP
CLR
will be enabled (see
Figure 19., page 19
and
Table 5., page 19
).
Note:
When using the inverting charge pump, the
user must also provide isolation in the form of two
additional small-signal power MOSFETs. These
will isolate the V
OUT
pin from both the negative
voltage generated by the charge pump during a
tamper condition, and from being pulled to ground
by the output of the charge pump when it is in shut-
down mode (SHDN = logic low). The gates of both
MOSFETs should be connected to TP
CLR
as
shown in
Figure 20., page 20
. One n-channel en-
hancement MOSFET should be placed between
the output of the inverting charge pump and the
V
OUT
of the M41ST87. The other MOSFET should
be an enhancement mode p-channel, and placed
between V
OUT
of the M41ST87 and V
CC
of the ex-
ternal SRAM. When TP
CLR
goes high after a
tamper condition occurs, the n-channel MOSFET
will turn on and the p-channel will turn off. During
normal operating conditions, TP
CLR
will be low
and the p-channel will be on, while the n-channel
will be off.
Table 4. Tamper Detection Current (Normally Closed - TCM
X
= '0')
Note: 1. When calculating battery lifetime, this current should be added to I
BAT
current listed in
Table 16., page 35
.
2. Per Tamper Detect Input
TDS
X
TCHI/TCLO
X
Tamper Circuit Mode
Current at 3.0V (typ)
(1,2)
Unit
0
0
Continuous Monitoring / 10M
pull-up/-down
0.3
μA
0
1
Continuous Monitoring / 1M
pull-up/-down
3.0
μA
1
0
Sampling (1Hz) / 10M
pull-up/-down
0.3
nA
1
1
Sampling (1Hz) / 1M
pull-up/-down
3.0
nA
相關PDF資料 |
PDF描述 |
|---|---|
| M41ST87WMX6TR | 5.0, 3.3, or 3.0V, 1280 bit (160 x8) Secure Serial RTC and NVRAM Supervisor with Tamper Detection |
| M41ST95Y | 5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
| M41ST95YMX6 | TWO-HEADED HOOD-COVER ONL |
| M41ST95YMX6E | TWO HEADED HOOD COVER |
| M41ST95YMX6F | TWO HEADED HOOD KIT M/M |
相關代理商/技術參數 |
參數描述 |
|---|---|
| M41ST87WMX6F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 V and 3.3/3.0 V secure serial RTC and NVRAM supervisor with tamper detection and 128 bytes of clearable NVRAM |
| M41ST87WMX6TR | 功能描述:實時時鐘 Serial 1280 (160x8) RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| M41ST87WSS6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 V and 3.3/3.0 V secure serial RTC and NVRAM supervisor with tamper detection and 128 bytes of clearable NVRAM |
| M41ST87WSS6F | 功能描述:實時時鐘 128 NVRAM Serial RTC 3.0 to 3.6 Vcc RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| M41ST87Y | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0, 3.3, or 3.0V, 1280 bit (160 x8) Secure Serial RTC and NVRAM Supervisor with Tamper Detection |
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