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參數(shù)資料
| 型號： | M41ST87WMX6 |
| 廠商： | 意法半導體 |
| 英文描述： | RECTIFIER SCHOTTKY SINGLE 10A 25V 200A-Ifsm 0.45Vf 1A-IR D2PAK 50/TUBE |
| 中文描述： | 5.0，3.3，或3.0V，1280位（160 × 8）安全串行時鐘和NVRAM篡改檢測與監(jiān)控 |
| 文件頁數(shù)： | 14/40頁 |
| 文件大小： | 610K |
| 代理商： | M41ST87WMX6 |
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M41ST87Y, M41ST87W
14/40
Data Retention Mode
With valid V
CC
applied, the M41ST87Y/W can be
accessed as described above with READ or
WRITE Cycles. Should the supply voltage decay,
the M41ST87Y/W will automatically deselect,
write protecting itself (and any external SRAM)
when V
CC
falls between V
PFD
(max) and
V
PFD
(min) (see
Figure
17., page 36
). This is accomplished by internally
inhibiting access to the clock registers. At this
time, the Reset pin (RST) is driven active and will
remain active until V
CC
returns to nominal levels.
External RAM access is inhibited in a similar man-
ner by forcing E
CON
to a high level. This level is
within 0.2 volts of the V
BAT
. E
CON
will remain at
this level as long as V
CC
remains at an out-of-tol-
erance condition. When V
CC
falls below the Bat-
tery Back-up Switchover Voltage (V
SO
), power
input is switched from the V
CC
pin to the battery,
and the clock registers and external SRAM are
maintained from the attached battery supply.
All outputs become high impedance. The V
OUT
pin
is capable of supplying 100μA (for M41ST87W) or
150μA (for M41ST87Y) of current to the attached
memory with less than 0.3 volts drop under this
condition. On power up, when V
CC
returns to a
nominal value, write protection continues for t
rec
by inhibiting E
CON
. The RST signal also remains
active during this time (see
Figure 27., page 36
).
Note:
Most low power SRAMs on the market to-
day can be used with the M41ST87Y/W RTC SU-
PERVISOR. There are, however some criteria
which should be used in making the final choice of
an SRAM to use. The SRAM must be designed in
a way where the chip enable input disables all oth-
er inputs to the SRAM. This allows inputs to the
M41ST87Y/W and SRAMs to be “Don’t Care”
once V
CC
falls below V
PFD
(min). The SRAM
should also guarantee data retention down to
V
CC
=2.0 volts. The chip enable access time must
be sufficient to meet the system needs with the
chip enable output propagation delays included. If
the SRAM includes a second chip enable pin (E2),
this pin should be tied to V
OUT
.
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0 volts. Manufacturers
generally specify a typical condition for room tem-
perature along with a worst case condition (gener-
ally at elevated temperatures). The system level
requirements will determine the choice of which
value to use. The data retention current value of
the SRAMs can then be added to the I
BAT
value of
the M41ST87Y/W to determine the total current re-
quirements for data retention. The available bat-
tery capacity for the battery of your choice can
27., page 36
,
Table
then be divided by this current to determine the
amount of data retention available.
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
Tamper Detection Circuit
The M41ST87Y/W provides two independent in-
put pins, the Tamper Pin 1 Input (TP1
IN
) and
Tamper Pin 2 Input (TP2
IN
), which can be used to
monitor two separate signals which can result in
the associated setting of the Tamper Bits (TB1
and/or TB2, in Flag Register 0Fh) if the Tamper
Enable Bits (TEB1 and/or TEB2) are enabled, for
the respective Tamper 1 or Tamper 2. The TP1
IN
Pin or TP2
IN
Pin may be set to indicate a tamper
event has occurred by either 1) closing a switch to
ground or V
OUT
(Normally Open), or by 2) opening
a switch that was previously closed to ground or
V
OUT
(Normally Closed), depending on the state
of the TCM
X
Bits and the TPM
X
Bits in the Tamper
Register (14h and/or 15h).
Tamper Register Bits (Tamper 1 and Tamper 2)
Tamper Enable Bits (TEB1 and TEB2).
When
set to a logic '1,' this bit will enable the Tamper De-
tection Circuit. This bit must be set to '0' in order to
clear the associated Tamper Bits (TB
X
, in 0Fh).
Note:
TEB
X
should be reset whenever the Tamper
Detect condition is modified.
Tamper Bits (TB1 and TB2).
If the TEB
X
Bit is
set, and a tamper condition occurs, the TB
X
Bit will
be set to '1.' This bit is “Read-only” and is reset
only by setting the TEB
X
Bit to '0.' These bits are
located in the Flags Register 0Fh.
Tamper Interrupt Enable Bits (TIE1 and TIE2).
If this bit is set to a logic '1,' the IRQ/OUT pin will
be activated when a tamper event occurs. This
function is also valid in battery back-up if the ABE
Bit (Alarm in Battery Back-up) is also set to '1' (see
Figure 15., page 16
).
Note:
In order to avoid an inadvertent activation of
the IRQ/OUT pin due to a prior tamper event, the
Flag Register (0Fh) should be read prior to reset-
ting the TEB
X
Bit.
Tamper Connect Mode Bit (TCM1 and TCM2).
This bit indicates whether the position of the exter-
nal switch selected by the user is in the Normally
Open
(TCM
X
= '1')
or
(TCM
X
= '0') position (see
Figure 14., page 15
and
Figure 16., page 16
).
Tamper Polarity Mode Bits (TPM1 and TPM2).
The state of this bit indicates whether the Tamper
Pin Input will be taken high (to V
OUT
if TPM
X
= '1')
or low (to V
SS
if TPM
X
= '0') during a tamper event
(see
Figure
14., page 15
16., page 16
).
Normally
Closed
and
Figure
相關PDF資料 |
PDF描述 |
|---|---|
| M41ST87WMX6TR | 5.0, 3.3, or 3.0V, 1280 bit (160 x8) Secure Serial RTC and NVRAM Supervisor with Tamper Detection |
| M41ST95Y | 5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
| M41ST95YMX6 | TWO-HEADED HOOD-COVER ONL |
| M41ST95YMX6E | TWO HEADED HOOD COVER |
| M41ST95YMX6F | TWO HEADED HOOD KIT M/M |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M41ST87WMX6F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 V and 3.3/3.0 V secure serial RTC and NVRAM supervisor with tamper detection and 128 bytes of clearable NVRAM |
| M41ST87WMX6TR | 功能描述:實時時鐘 Serial 1280 (160x8) RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| M41ST87WSS6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 V and 3.3/3.0 V secure serial RTC and NVRAM supervisor with tamper detection and 128 bytes of clearable NVRAM |
| M41ST87WSS6F | 功能描述:實時時鐘 128 NVRAM Serial RTC 3.0 to 3.6 Vcc RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| M41ST87Y | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0, 3.3, or 3.0V, 1280 bit (160 x8) Secure Serial RTC and NVRAM Supervisor with Tamper Detection |
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