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參數(shù)資料
| 型號： | M40Z300MQ |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | NVRAM CONTROLLER for up to EIGHT LPSRAM |
| 中文描述： | NVRAM中多達8個LPSRAM控制器 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 128K |
| 代理商： | M40Z300MQ |
3/16
M40Z300, M40Z300W
Table 2. Absolute Maximum Ratings
(1)
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
CAUTION:
Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION:
Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
0 to 70
°C
T
STG
Storage Temperature (V
CC
Off)
SNAPHAT
SOIC
–40 to 85
–55 to 125
°C
V
IO
Input or Output Voltages
–0.3 to V
CC
+0.3
V
V
CC
Supply Voltage
M40Z300
M40Z300W
–0.3 to 7
–0.3 to 4.6
V
I
O
Output Current
20
mA
P
D
Power Dissipation
1
W
OPERATION
The M40Z300/W, as shown in Figure 4, can con-
trol up to four (eight, if placed in parallel) standard
low-power SRAMs. These SRAMs must be config-
ured to have the chip enable input disable all other
input signals. Most slow, low-power SRAMs are
configured like this, however many fast SRAMs
are not. During normal operating conditions, the
conditioned chip enable (E1
CON
to E4
CON
) output
pins follow the chip enable (E) input pin with timing
shown in Table 7. An internal switch connects V
CC
to
This switch has a voltage drop of less than 0.3V
(I
OUT1
).
When V
CC
degrades during a power failure,
E1
CON
to E4
CON
are forced inactive independent
of E. In this situation, the SRAM is unconditionally
write protected as V
CC
falls below an out-of-toler-
ance threshold (V
PFD
). For the M40Z300 the pow-
er fail detection value associated with V
PFD
is
selected by the Threshold Select (THS) pin and is
shown in Table 6A. For the M40Z300W, the THS
pin selects both the supply voltage and V
PFD
as
shown in Table 6B.
Note
: In either case, THS pin must be connected
to either V
SS
or V
OUT
.
V
OUT
.
If chip enable access is in progress during a power
fail detection, that memory cycle continues to com-
pletion before the memory is write protected. If the
memory cycle is not terminated within time t
WPT
,
E1
CON
to E4
CON
are unconditionally driven high,
write protecting the SRAM. A power failure during
a write cycle may corrupt data at the currently ad-
dressed location, but does not jeopardize the rest
of the SRAM’s contents. At voltages below V
PFD
(min), the user can be assured the memory will be
write protected within the Write Protect Time
(t
WPT
) provided the V
CC
fall time exceeds t
F
(See
Table 7).
As V
CC
continues to degrade, the internal switch
disconnects V
CC
and connects the internal battery
to V
OUT
. This occurs at the switchover voltage
(V
SO
). Below the V
SO
, the battery provides a volt-
age V
OHB
to the SRAM and can supply current
I
OUT2
(see Table 6A/6B).
When V
CC
rises above V
SO
, V
OUT
is switched
back to the supply voltage. Outputs E1
CON
to
E4
CON
are held inactive for t
CER
(120ms maxi-
mum) after the power supply has reached V
PFD
,
independent of the E input, to allow for processor
stabilization (see Figure 6).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M40Z300MQ1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:NVRAM CONTROLLER for up to EIGHT LPSRAM |
| M40Z300MQ1E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5 V or 3 V NVRAM supervisor for up to 8 LPSRAMs |
| M40Z300MQ1F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V or 3V NVRAM supervisor for up to 8 LPSRAMs |
| M40Z300MQ1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:NVRAM CONTROLLER for up to EIGHT LPSRAM |
| M40Z300MQ6E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V or 3V NVRAM supervisor for up to 8 LPSRAMs |
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