![](http://datasheet.mmic.net.cn/370000/M39832-T12WNE1T_datasheet_16706546/M39832-T12WNE1T_9.png)
Mne.
Instr.
Cyc.
1st
Cyc.
2nd
Cyc.
3rd
Cyc.
4th
Cyc.
5th
Cyc.
6th
Cyc.
7th
Cyc.
RD
(2,4)
Read/Reset
Memory
Array
1+
Addr.
(3,7)
X
Read Memory Array until a new write cycle is initiated.
Data
F0h
3+
(3,7)
Byte
AAAAh
5555h
AAAAh
Read Memory Array until a new write
cycle is initiated.
Word
5555h
2AAAh
5555h
Data
AAh
55h
F0h
AS
(4)
Auto Select
3+
(3,7)
Byte
AAAAh
5555h
AAAAh
Read Electronic Signature or Block
Protection Status until a new write
cycle is initiated. See Note 5 and 6.
Word
5555h
2AAAh
5555h
Data
AAh
55h
90h
PG
Program
4
(3,7)
Byte
AAAAh
5555h
AAAAh Program
Address
Read Data Polling or
Toggle Bit until Program
completes.
Word
5555h
2AAAh
5555h
Data
AAh
55h
A0h
Program
Data
BE
Block Erase
6
(3,7)
Byte
AAAAh
5555h
AAAAh
AAAAh
5555h
Block
Address
Additiona
l Block
Word
5555h
2AAAh
5555h
5555h
2AAAh
Data
AAh
55h
80h
AAh
55h
30h
30h
FAE
Flash Array
Erase
6
(3,7)
Byte
AAAAh
5555h
AAAAh
AAAAh
5555h
AAAAh
Note 9
Word
5555h
2AAAh
5555h
5555h
2AAAh
5555h
Data
AAh
55h
80h
AAh
55h
10h
ES
(10)
Erase
Suspend
1
Addr.
(3,7)
X
Read until Toggle stops, then read all the data needed
from any Block(s) not being erased then Resume Erase.
Data
B0h
ER
Erase
Resume
1
Addr.
(3,7)
X
Read Data Polling or Toggle Bits until Erase completes
or Erase is suspended another time
Data
30h
Notes:
1. Commands not interpreted in this table will default to read array mode.
2. A wait of t
is necessary after a Read/Reset command if the memory was in an Erase or Program mode
before starting any new operation (see Table 14 and Figure 9).
3. X = Don’t Care.
4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after
the command cycles.
5. Signature Address bits A0, A1, at V
IL
will output Manufacturer code (20h). Address bits A0 at V
IH
and A1, at V
IL
will output
Flash code.
6. Block Protection Address: A0, at V
, A1 at V
and A15-A18 within the Block will output the Block Protection status.
7. For Coded cycles address inputs A11-A18 are don’t care.
8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout status
can be verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered, read Data Polling
or Toggle bit until Erase is completed or suspended.
9. Read Data Polling, Toggle bits or FRB until Erase completes.
10.During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.
Table 5A. Flash Instructions (EF=0, EE=1)
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M39832