參數(shù)資料
型號(hào)： M39832-T12WNE6T
廠商： 意法半導(dǎo)體
英文描述： TVS UNI-DIR 33V 600W DO-15
中文描述： 單芯片8兆1兆x8或512KB的x16閃存和256千位并行EEPROM存儲(chǔ)器
文件頁(yè)數(shù)： 15/36頁(yè)
文件大?。?/td> 253K
代理商： M39832-T12WNE6T
Read the EEPROM Identifier
The EEPROM identifier (64 bytes, user defined)
can be read with a single Read operation with A6
= ’0’ and A9 = V
ID
(See Table 6).
When accessing the 64 Bytes of EEPROM Identi-
fier, the only LSB addresses are decoded. The LSB
addresses are A0 to A5 when BYTE = ’1’ (x16) and
A–1 to A4 when BYTE = ’0’ (x8). Each Byte of the
EEPROM identifier can be individually accessed in
read or write mode.
Read the OTP Row
The OTP row is mapped in the EEPROM array
(EE = ’0’, EF = ’1’). Read of the OTP row (64 bytes)
is by an instruction (ROTP) composed of three
specific Write operations of data bytes at three
specific memory locations (each location in a dif-
ferent page) before reading the OTP row content
(See Table 5B).
When accessing the OTP row, only the LSB ad-
dresses are decoded and A6 must be ’0’. The LSB
addresses are A0 to A5 when BYTE = ’1’ (x16) and
A–1 to A4 when BYTE = ’0’ (x8).
Each Read of the OTP row has to be followed by
the (RT) Return instruction (See Table 5B).
Read the Flash Block Protection Status
Reading the Flash block protection status is by a
read operation immediatly following the AS instruc-
tion (See Table 5A and Table 8). A12-A18 define
the Flash block whose protection has to be veri-
fied. This Read operation will output a 01h if the
Flash block is protected and a 00h if the Flash block
is not protected.
The Flash block protection status can also be
verified with a single Read operation (see chapter:
Flash array specific features), with V
ID
on A9 (See
Table 6 and Table 8).
Read the Status Bits
The M39832 provides several Write operation
status flags which may be used to minimize the
application write (or erase or program) time. These
signals are available on the I/O port bits when
programming (or erasing) are in progress. It should
be noted that the Ready/Busy pins also reflects the
status of the EEPROM Write and the Flash Pro-
gramming/Erasing.
Data Polling flag, DQ7.
When Erasing or Pro-
gramming into the Flash block (or when Writing into
the EEPROM block), bit DQ7 outputs the comple-
ment of the bit being entered for Program-
ming/Writing on DQ7. Once the Program instruc-
tion or the Write operation is performed, the true
logic value is read on DQ7 (in a Read operation).
Flash memory block specific features:
– Data Polling is effective after the fourth W pulse
(for programming) or after the sixth W pulse (for
Erase). It must be performed at the address
being programmed or at an address within the
Flash sector being erased.
– During an Erase instruction, DQ7 outputs a ’0’.
After completion of the instruction, DQ7 will out-
put the last bit programmed (that is a ’1’ after
erasing).
– if the byte to be programmed is in a protected
Flash sector, the instruction is ignored.
– If all the Flash sectors to be erased are pro-
tected, DQ7 will be set to ’0’ for about 100
μ
s, and
then return to the previous addressed byte. No
erasure will be performed.
– if all sectors are protected, a Bulk Erase instruc-
tion is ignored.
Toggle flag, DQ6.
The M39832 also offers another
way for determining when the EEPROM write or
the Flash memory Program instruction is com-
pleted. During the internal Write operation, the DQ6
will toggle from ’0’ to ’1’ and ’1’ to ’0’ on subsequent
attempts to read any byte of the memory, when
either G , EE or EF is low.
When the internal cycle is completed the toggling
will stop and the data read on DQ0-DQ7 is the
addressed memory byte. The device is now acces-
sible for a new Read or Write operation. The opera-
tion is completed when two successive reads yield
the same output data.
Flash memory block specific features:
a. The Toggle bit is effective after the fourth W pulse
(for programming) or after the sixth W pulse (for
Erase).
b. If the byte to be programmed belongs to a pro-
tected Flash sector, the instruction is ignored and:
– if all the Flash sectors selected for erasure
are protected, DQ6 will toggle to ’0’ for about
100
μ
s, and then return to the previous ad-
dressed byte.
– if all sectors are protected, the Bulk Erase in-
struction is ignored.
15/36
M39832
相關(guān)PDF資料
PDF描述
M39832-T15WNE6T TVS BI-DIR 33V 600W DO-15
M39832-B12WNE6T RECTIFIER, BRIDGE, 600V, 6A, PB-6
M39832-B15WNE6T TVS UNI-DIR 51V 600W DO-15
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M4565 LINEAR INTEGRATED CIRCUIT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M39832-T15WNE1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Single Chip 8 Mbit 1Mb x8 or 512Kb x16 Flash and 256 Kbit Parallel EEPROM Memory
M39832-T15WNE6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Single Chip 8 Mbit 1Mb x8 or 512Kb x16 Flash and 256 Kbit Parallel EEPROM Memory
M3986 SL001 制造商:Alpha Wire Company 功能描述:CBL 10PR 24AWG SLT 1000'
M3986 SL002 制造商:Alpha Wire Company 功能描述:CBL 10PR 24AWG SLT 500'
M3986 SL005 制造商:Alpha Wire Company 功能描述:CBL 10PR 24AWG SLT 100'
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