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參數(shù)資料
| 型號(hào)： | M38C37ECMFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁(yè)數(shù)： | 8/221頁(yè) |
| 文件大?。?/td> | 1919K |
| 代理商： | M38C37ECMFP |
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Programming Model
Chip-Select Logic
6-17
CSCTRL1
Chip-Select Control Register 1
0x(FF)FFF10A
BIT 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT 0
EUP
EN
SR
16
EW
S0
DW
S0
CW
S0
BW
S0
AW
S0
DSI
Z3
DUP
S2
CUP
S2
BUP
S2
TYPE
rw
RESET
0
00
0
0x0000
Table 6-12. Chip-Select Control Register 1 Description
Name
Description
Setting
Reserved
Bit 15
Reserved
This bit is reserved and should be set to 0.
EUPEN
Bit 14
Extra UPSIZ Bit Enable—This bit enables the
BUPS2, CUPS2, and DUPS2 bits to work with
the corresponding UPSIZ configuration bits.
Hence, it provides a larger dynamic range with
smaller granularity for the unprotected memory
sizing.
0 = EUPEN bit not set.
1 = EUPEN bit set.
SR16
Bit 13
16-Bit SRAM Enable—This bit enables the
use of 16-bit SRAM in chip-select group B
memory space. It determines the functions of
the UWE/UB and LWE/LB pins in CSB
read/write cycles.
0 = UWE and LWE are selected for all CSB
read/write cycles.
1 = UB and LB are selected for all CSB
read/write cycles.
EWSO
Bit 12
Emulation Chip-Select Wait State
Bit 0—This bit is the lowest significant bit of
the EMU wait state register.
Refer to Table 6-11 on page 6-16 on the emu-
lation chip-select register for the wait state set-
ting.
DWSO
Bit 11
CSD Wait State Bit 0—This bit is the lowest
significant bit of the CSD wait state register.
Refer to Table 6-10 on page 6-14 on the
chip-select register D for the wait state setting.
CWSO
Bit 10
CSC Wait State Bit 0—This bit is the lowest
significant bit of the CSC wait state register.
Refer to Table 6-9 on page 6-12 on the
chip-select register C for the wait state setting.
BWSO
Bit 9
CSB Wait State Bit 0—This bit is the lowest
significant bit of the CSB wait state register.
Refer to Table 6-8 on page 6-10 on the
chip-select register B for the wait state setting.
AWS0
Bit 8
CSA Wait State Bit 0—This bit is the lowest
significant bit of the CSA wait state register.
Refer to Table 6-7 on page 6-8 on the
chip-select register A for the wait state setting.
Reserved
Bit 7
Reserved
This bit is reserved and should be set to 0.
DSIZ3
Bit 6
Size Bit 3 for DRAM Chip-Select Address-
ing Space—When set, this bit extends the
DRAM size.
If SIZ[2:0] = 000, the CSD0 and CSD1 spaces
are each 8 Mbyte. For 001, each space is
16 Mbyte. Only valid when the DRAM bit of the
CSD register is set.
Reserved
Bit 5
Reserved
This bit is reserved and should be set to 0.
DUPS2
Bit 4
UPSIZ Bit 2 for CSD Register—This is the
most significant bit for UPSIZ[2:0] when the
EUPEN bit is set.
For information on calculating unprotected
memory size, see Example 6-1 on page 6-18.
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