29
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
Fig. 23 Structure of Timer X, Y related registers
Timer X mode register
(TXM: address 002F16)
Timer X operating mode bits
b2 b1 b0
0 0 0 : Timer mode
0 0 1 : Pulse output mode
0 1 0 : IGBT output mode
0 1 1 : PWM mode
1 0 0 : Event counter mode
1 0 1 : Pulse width measurement mode
Timer X write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer X count source selection bit
0 : Frequency divider output
1 : f(XCIN)
Data for control of event counter window
0 : Event count enabled
1 : Event count disabled
Timer X count stop bit
0 : Count operation
1 : Count stop
Timer X output selection bit (P35)
0 : I/O port
1 : Timer X output
b7
b0
Timer X control register
(TXCON: address 0FF416)
Noise filter sampling clock selection bit
0 : f(XIN)/2
1 : f(XIN)/4
External trigger delay time selection bits
b2 b1
0 0 : Not delayed
0 1 : (4/f(XIN))
s
1 0 : (8/f(XIN))
s
1 1 : (16/f(XIN))
s
Timer X output control bit 1 (P51)
0 : Not used
1 : INT1 interrupt used
Timer X output control bit 2 (P34)
0 : Not used
1 : INT2 interrupt used
Timer X output edge switch bit
0 : Start at “L” output
1 : Start at “H” output
CNTR0 active edge switch bits
b7 b6
0 0 : Count at rising edge in event counter mode
Falling edge active for CNTR0 interrupt
Measure “H” pulse width in pulse width measurement mode
0 1 : Count at falling edge in event counter mode
Rising edge active for CNTR0 interrupt
Measure “L” pulse width in pulse width measurement mode
1 0 : Count at both edges in event counter mode
Both edges active for CNTR0 interrupt
1 1 : Count at both edges in event counter mode
Both edges active for CNTR0 interrupt
b7
b0
Timer XY frequency division selection register
(PREXY: address 0FF716)
Timer X frequency division selection bits
b2 b1 b0
0 0 0 : 1/16 f(XIN) or 1/16 f(XCIN)
0 0 1 : 1/1 f(XIN) or 1/1 f(XCIN)
0 1 0 : 1/2 f(XIN) or 1/2 f(XCIN)
0 1 1 : 1/32 f(XIN) or 1/32 f(XCIN)
1 0 0 : 1/64 f(XIN) or 1/64 f(XCIN)
1 0 1 : 1/128 f(XIN) or 1/128 f(XCIN)
1 1 0 : 1/256 f(XIN) or 1/256 f(XCIN)
1 1 1 : 1/1024 f(XIN) or 1/1024 f(XCIN)
Timer Y frequency division selection bits
b5 b4 b3
0 0 0 : 1/16 f(XIN) or 1/16 f(XCIN)
0 0 1 : 1/1 f(XIN) or 1/1 f(XCIN)
0 1 0 : 1/2 f(XIN) or 1/2 f(XCIN)
0 1 1 : 1/32 f(XIN) or 1/32 f(XCIN)
1 0 0 : 1/64 f(XIN) or 1/64 f(XCIN)
1 0 1 : 1/128 f(XIN) or 1/128 f(XCIN)
1 1 0 : 1/256 f(XIN) or 1/256 f(XCIN)
1 1 1 : 1/1024 f(XIN) or 1/1024 f(XCIN)
Not used (returns “0” when read)
b7
b0
Timer Y mode register
(TYM: address 003016)
Real time port control bit
0 : Real time port function invalid
1 : Real time port functin valid
P46 data for real time port
P47 data for real time port
Timer Y count source selection bit
0 : Frequency divider output
1 : f(XCIN)
Timer Y operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Period measurement mode
1 0 : Event counter mode
1 1 : Pulse width HL continuous measurement mode
CNTR1 active edge switch bit
0 : Count at rising edge in event counter mode
Measure falling period in period measurement mode
Falling edge active for CNTR1 interrupt
1 : Count at falling edge in event counter mode
Measure rising period in period measurement mode
Rising edge active for CNTR1 interrupt
Timer Y count stop bit
0 : Count operation
1 : Count stop
b7
b0
Timer Y mode register 2
(TYM2: address 0FFB16)
Timer Y write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Not used (returns “0” when read)
b7
b0