參數(shù)資料
型號： M38B79MFH-A055
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 28/109頁
文件大小： 1559K
代理商： M38B79MFH-A055
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
28
SERIAL I/O
Serial I/O1
Serial I/O1 is used as the clock synchronous serial I/O and has an
ordinary mode and an automatic transfer mode. In the automatic
transfer mode, serial transfer is performed through the serial I/O
automatic transfer RAM which has up to 256 bytes (addresses
Fig. 21 Block diagram of serial I/O1
0F00
16
to 0FFF
16
).
The PB
1
/S
RDY1
, PB
2
/S
BUSY1
, and PB3/S
STB1
pins each have a
handshake I/O signal function and can select either
“
H
”
active or
“
L
”
active for active logic.
Main
data bus
Serial I/O1
automatic transfer
controller
L
d
o
a
c
t
a
a
l
b
u
s
Serial I/O automatic
transfer RAM
(0F00
16
to 0FFF
16
)
S
n
e
r
o
r
i
a
r
l
e
I
g
/
O
i
s
1
t
e
c
o
t
l
r
3
X
C
I
N
X
I
N
Internal system
clock selection bit
Serial I/O1
automatic transfer
data pointer
Address decoder
M
b
a
s
i
n
a
d
d
r
e
s
s
u
Local address
bus
“
1
”
“
0
”
1/8
1/16
1/32
1
6
1
1
1/256
/
/
4
2
8
S
i
n
e
t
r
e
i
r
a
r
l
u
I
p
/
O
t
1
r
e
q
u
e
s
t
PB
2
latch
“
0
”
Serial I/O1 counter
S
c
y
i
r
n
c
c
u
h
i
t
r
o
n
o
u
s
S
s
s
e
y
e
r
i
c
a
l
r
i
I
o
o
/
O
n
n
1
o
b
u
i
n
l
e
h
c
s
t
c
l
o
c
“
0
”
k
t
“
1
Serial I/O1 clock
pin selection bit
”
P
B
1
l
a
t
c
h
P
B
4
/
S
C
L
K
1
1
“
0
”
“
1
“
1
”
”
S
C
L
K
1
In
c
t
o
e
c
r
k
n
a
s
l
e
s
l
e
y
n
c
c
i
o
h
n
r
o
b
n
i
o
t
s
u
s
l
t
PB
3
latch
P
B
2
/
S
B
U
PB
1
/S
RDY1
PB
2
/S
BUSY1
pin control bit
S
Y
1
P
B
3
/
S
S
P
p
T
B
1
(
P
B
3
/
S
S
T
B
1
p
i
n
c
o
n
t
r
o
l
b
i
t
)
S
e
s
r
t
i
a
a
l
u
t
r
s
a
n
f
l
s
f
e
r
t
a
g
“
0
”
“
1
”
“
1
”
P
B
1
/
S
R
D
Y
1
“
0
”
“
1
”
P
B
4
l
a
t
c
h
PB
5
/S
OUT1
P
B
6
/
S
I
N
1
PB
5
latch
Serial I/O1 register (8)
“
0
”
“
1
”
S
e
r
i
a
l
t
r
a
n
s
f
e
r
s
e
l
e
c
t
i
o
n
b
i
t
s
1
/
2
D
i
v
i
d
e
r
1
/
4
P
B
0
/
S
C
L
K
1
2
“
0
”
PB
0
latch
“
0
”
“
1
S
e
p
i
n
”
i
s
“
0
”
“
1
”
r
a
l
l
I
e
/
O
c
1
t
i
c
n
l
o
b
c
i
k
t
s
e
o
B
1
/
i
n
S
R
c
o
D
t
Y
o
1
l
P
b
B
2
/
t
S
B
U
S
Y
1
n
r
i
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