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參數(shù)資料
| 型號： | M38B79MFH-A055 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 23/109頁 |
| 文件大?。?/td> | 1559K |
| 代理商： | M38B79MFH-A055 |
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
23
TIMERS
8-Bit Timer
The 38B7 group has six built-in 8-bit timers : Timer 1, Timer 2, Timer
3, Timer 4, Timer 5, and Timer 6.
Each timer has the 8-bit timer latch. All timers are down-counters.
When the timer reaches
“
00
16
”
, an underflow occurs with the next
count pulse. Then the contents of the timer latch is reloaded into the
timer and the timer continues down-counting. When a timer
underflows, the interrupt request bit corresponding to that timer is set
to
“
1
”
.
The count can be stopped by setting the stop bit of each timer to
“
1
”
.
The internal system clock can be set to either the high-speed mode
or low-speed mode with the CPU mode register. At the same time,
the timer internal count source is switched to either f(X
IN
) or f(X
CIN
).
G
Timer 1, Timer 2
The count sources of timer 1 and timer 2 can be selected by setting
the timer 12 mode register. A rectangular waveform of timer 1 under-
flow signal divided by 2 can be output from the P7
5
/T1
OUT
pin. The
active edge of the external clock CNTR
0
can be switched with the bit
6 of the interrupt edge selection register.
At reset or when executing the STP instruction, all bits of the timer 12
mode register are cleared to
“
0
”
, timer 1 is set to
“
FF
16
”
, and timer 2
is set to
“
01
16
”
.
G
Timer 3, Timer 4
The count sources of timer 3 and timer 4 can be selected by setting
the timer 34 mode register. A rectangular waveform of timer 3 under-
flow signal divided by 2 can be output from the P7
6
/T3
OUT
pin. The
active edge of the external clock CNTR
1
can be switched with the bit
7 of the interrupt edge selection register.
G
Timer 5, Timer 6
The count sources of timer 5 and timer 6 can be selected by setting
the timer 56 mode register. A rectangular waveform of timer 6 under-
flow signal divided by 2 can be output from the P7
4
/PWM
1
pin.
G
Timer 6 PWM
1
Mode
Timer 6 can output a PWM rectangular waveform with
“
H
”
duty cycle
n/(n+m) from the P7
4
/PWM
1
pin by setting the timer 56 mode regis-
ter (refer to Figure 18). The n is the value set in timer 6 latch (address
0025
16
) and m is the value in the timer 6 PWM register (address
0027
16
). If n is
“
0,
”
the PWM output is
“
L
”
, if m is
“
0
”
, the PWM output
is
“
H
”
(n = 0 is prior than m = 0). In the PWM mode, interrupts occur
at the rising edge of the PWM output.
Fig. 16 Structure of timer related registers
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