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參數(shù)資料
| 型號(hào)： | M38B59MFH-P113FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 35/69頁 |
| 文件大?。?/td> | 1011K |
| 代理商： | M38B59MFH-P113FP |
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MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
35
PRELIMINARY
Notice: This s not a final specification.
Some parametric imits are subject to change.
[Serial I/O2 Control Register] SIO2CON (001D
16
)
The serial I/O2 control register contains eight control bits for serial
I/O2 functions.
[UART Control Register] UARTCON (0017
16
)
This is a 5 bit register containing four control bits (b0 to b3), which
are valid when UART is selected and set the data format of data
receive/transfer, and one control bit (b4), which is always valid and
sets the output structure of the P5
5
/TxD pin.
[Serial I/O2 Status Register] SIO2STS (001E
16
)
The read-only serial I/O2 status register consists of seven flags (b0
to b6) which indicate the operating status of the serial I/O2 function
and various errors. Three of the flags (b4 to b6) are only valid in the
UART mode. The receive buffer full flag (b1) is cleared to “0” when
the receive buffer is read.
The error detection is performed at the same time data is transferred
from the receive shift register to the receive buffer register, and the
receive buffer full flag is set. A writing to the serial I/O2 status regis-
ter clears error flags OE, PE, FE, and SE (b3 to b6, respectively).
Writing “0” to the serial I/O2 enable bit (SIOE : b7 of the serial I/O2
control register) also clears all the status flags, including the error
flags.
All bits of the serial I/O2 status register are initialized to “0” at reset,
but if the transmit enable bit (b4) of the serial I/O2 control register
has been set to “1,” the transmit shift register shift completion flag
(b2) and the transmit buffer empty flag (b0) become “1.”
[Serial I/O2 Transmit Buffer Register/Receive
Buffer Register] TB/RB (001F
16
)
The transmit buffer and the receive buffer are located in the same
address. The transmit buffer is write-only and the receive buffer is
read-only. If a character bit length is 7 bits, the MSB of data stored in
the receive buffer is "0".
[Baud Rate Generator] BRG (0016
16
)
The baud rate generator determines the baud rate for serial transfer.
With the 8-bit counter having a reload register, the baud rate genera-
tor divides the frequency of the count source by 1/(n+1), where n is
the value written to the baud rate generator.
Fig. 38 Structure of Serial I/O2 Related Register
b7
b7
Transmit buffer empty flag (TBE)
Receive buffer full flag (RBF)
Transmit shift register shift completion flag (TSC)
Overrun error flag (OE)
Parity error flag (PE)
Framing error flag (FE)
Summing error flag (SE)
Not used (returns "1" when read)
Serial I/O2 status register
16
)
Serial I/O2 control register
16
)
b0
b0
b7
UART control register
16
)
Character length selection bit (CHAS)
Parity enable bit (PARE)
Parity selection bit (PARS)
Stop bit length selection bit (STPS)
5
/T
X
D P-channel output disable bit (POFF)
P5
IN
CIN
(depends on internal system clock)
BRG or X
CIN
7
/S
CLK22
RDY2
output pin.)
Serial I/O (P5
CLK22
(P5
6
/S
CLK21
pin is used as I/O port or S
Not used (return "1" when read)
b0
CIN
)/)/8 or f(X
CIN
)
BRG c) or f(X
IN
)/4 or f(X
CIN
CIN
)/4
Serial I/O2 synchronous clock selection bit (SCS)
RDY2
pin operates as ordinary I/O pin
7
S
7
pin operates as S
RDY2
output pin
Transmit interrupt source selection bit (TIC)
Transmit enable bit (TE)
Receive enable bit (RE)
Serial I/O2 mode selection bit (SIOM)
7
operate as ordinary I/O pins)
Serial I/O2 to P5
4
to P5
7
operate as serial I/O pins)
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