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參數(shù)資料
| 型號： | M38B59MFH-E111FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 66/69頁 |
| 文件大?。?/td> | 1011K |
| 代理商： | M38B59MFH-E111FP |
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MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
66
PRELIMINARY
Notice: This s not a final specification.
Some parametric imits are subject to change.
TIMING REQUIREMENTS
Table 16 Timing Requirements
(V
CC
= 4.0 to 5.5V, V
SS
= 0V, Ta = –20 to 85°C, unless otherwise noted)
Min.
2.0
238
60
60
20
5.0
5.0
4.0
1.6
1.6
80
80
0.95
400
400
200
200
Typ.
Max.
Symbol
Parameter
Limits
Unit
____________
t
W
(RESET)
t
C
(X
IN
)
t
WH
(X
IN
)
t
WL
(X
IN
)
t
C
(X
CIN
)
t
WH
(X
CIN
)
t
WL
(X
CIN
)
t
C
(CNTR)
t
WH
(CNTR)
t
WL
(CNTR)
t
WH
(INT)
t
WL
(INT)
t
C
(S
CLK
)
t
WH
(S
CLK
)
t
WL
(S
CLK
)
t
su
(S
CLK
–S
IN
)
t
h
(S
CLK
–S
IN
)
Reset input “L” pulse width
Main clock input cycle time (X
IN
input)
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub-clock input cycle time (X
CIN
input)
Sub-clock input “H” pulse width
Sub-clock input “L” pulse width
CNTR
0
, CNTR
1
input cycle time
CNTR
0
, CNTR
1
input “H” pulse width
CNTR
0
, CNTR
1
input “L” pulse width
INT
0
to INT
4
input “H” pulse width
INT
0
to INT
4
input “L” pulse width
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
Serial I/O input set up time
Serial I/O input hold time
μs
ns
ns
ns
μs
μs
μs
μs
μs
μs
ns
ns
μs
ns
ns
ns
ns
SWITCHING CHARACTERISTICS
Table 17 Switching Characteristics
(V
CC
= 4.0 to 5.5V, V
SS
= 0V, Ta = –20 to 85°C, unless otherwise noted)
Min.
Typ.
Max.
Symbol
Parameter
Limits
Unit
ns
ns
ns
ns
ns
ns
ns
μs
t
WH
(S
CLK
)
t
WL
(S
CLK
)
t
d
(S
CLK
–S
OUT
)
t
v
(S
CLK
–S
OUT
)
t
r
(S
CLK
)
t
f
(S
CLK
)
t
r
(Pch–strg)
t
r
(Pch–weak)
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time
Serial I/O output valid time
Serial I/O clock output rising time
Serial I/O clock output falling time
P-channel high-breakdown voltage
output rising time (Note 1)
P-channel high-breakdown voltage
output rising time (Note 2)
0.2 tc
40
40
55
1.8
t
C
(S
CLK
)/2–160
t
C
(S
CLK
)/2–160
0
Test conditions
C
L
= 100 pF
C
L
= 100 pF
C
L
= 100 pF
C
L
= 100 pF
C
L
= 100 pF
V
EE
= V
CC
–43 V
C
L
= 100 pF
V
EE
= V
CC
–43 V
Notes 1:
When bit 7 of the FLDC mode register (address 0EF4
16
) is at “0”.
2:
When bit 7 of the FLDC mode register (address 0EF4
16
) is at “1”.
Fig. 73 Circuit for Measuring Output Switching Characteristics
C
L
Serial I/O clock
output port
C
L
V
EE
High-breakdown
P-channel open-
drain output port
P5
2
/S
CLK11
,
P5
3
/S
CLK12
,
P5
6
/S
CLK21
,
P5
7
/S
CLK22
P0,P1,P2,
P3,P8
0–
P8
3
Note: Ports P2 and P8 need external resistors.
(Note)
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