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| 型號(hào)： | M38B59MFH-E111FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁(yè)數(shù)： | 10/69頁(yè) |
| 文件大?。?/td> | 1011K |
| 代理商： | M38B59MFH-E111FP |
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MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
10
PRELIMINARY
Notice: This s not a final specification.
Some parametric imits are subject to change.
I/O Ports
[Direction Registers] PiD
The 38B5 group has 55 programmable I/O pins arranged in eight
individual I/O ports (P0, P2, P4
0
–P4
6
, and P5–P9). The I/O ports
have direction registers which determine the input/output direction of
each individual pin. Each bit in a direction register corresponds to
one pin, and each pin can be set to be input port or output port. When
“0” is written to the bit corresponding to a pin, that pin becomes an
input pin. When “1” is written to that pin, that pin becomes an output
pin. If data is read from a pin set to output, the value of the port
output latch is read, not the value of the pin itself. Pins set to input
(the bit corresponding to that pin must be set to “0”) are floating and
the value of that pin can be read. If a pin set to input is written to, only
the port output latch is written to and the pin remains floating.
[High-Breakdown-Voltage Output Ports]
The 38B5 group microprocessors have 5 ports with high-breakdown-
voltage pins (ports P0–P3
and P8
0
–P8
3
). The high-breakdown-volt-
age ports have P-channel open-drain output with Vcc- 45 V of break-
down voltage. Each pin in ports P0, P1, and P3 has an internal pull-
down resistor connected to V
EE
. At reset, the P-channel output tran-
sistor of each port latch is turned off, so that it goes to V
EE
level (“L”)
by the pull-down resistor.
Writing “1” (weak drivability) to bit 7 of the FLDC mode register (ad-
dress 0EF4
16
) shows the rising transition of the output transistors for
reducing transient noise. At reset, bit 7 of the FLDC mode register is
set to “0” (strong drivability).
[Pull-up Control Register] PULL
Ports P5, P6
1
–P6
5
, P7, P8
4
–P8
7
and P9 have built-in programmable
pull-up resistors. The pull-up resistors are valid only in the case that
the each control bit is set to “1” and the corresponding port direction
registers are set to input mode.
Fig. 8 Structure of Pull-up Control Registers
(PULL1 and PULL2)
0: No pull-up
1: Pull-up
Pull-up control register 2
(PULL2 : address 0EF1
16
)
P7
0
, P7
1
pull-up control bit
P7
2
, P7
3
pull-up control bit
P7
4
, P7
5
pull-up control bit
P7
6
, P7
7
pull-up control bit
P8
4
, P8
5
pull-up control bit
P8
6
, P8
7
pull-up control bit
P9
0
, P9
1
pull-up control bit
Not used
(returns “0” when read)
b7
b0
0: No pull-up
1: Pull-up
Pull-up control register 1
(PULL1 : address 0EF0
16
)
P5
0
, P5
1
pull-up control bit
P5
2
, P5
3
pull-up control bit
P5
4
, P5
5
pull-up control bit
P5
6
, P5
7
pull-up control bit
P6
1
pull-up control bit
P6
2
, P6
3
pull-up control bit
P6
4
, P6
5
pull-up control bit
Not used
(returns “0” when read)
b7
b0
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