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參數(shù)資料
| 型號： | M38B59MFH-E107FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 33/69頁 |
| 文件大?。?/td> | 1011K |
| 代理商： | M38B59MFH-E107FP |
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MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
33
PRELIMINARY
Notice: This s not a final specification.
Some parametric imits are subject to change.
G
Serial I/O2
Serial I/O2 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation during serial I/O2 operation.
(1) Clock Synchronous Serial I/O Mode
The clock synchronous serial I/O mode can be selected by setting
the serial I/O2 mode selection bit (b6) of the serial I/O2 control reg-
Fig. 35 Operation of Clock Synchronous Serial I/O2 Function
Fig. 34 Block Diagram of Clock Synchronous Serial I/O2
ister (address 001D
16
) to “1.” For clock synchronous serial I/O, the
transmitter and the receiver must use the same clock for serial I/O2
operation. If an internal clock is used, transmit/receive is started by
a write signal to the serial I/O2 transmit/receive buffer register (TB/
RB) (address 001F
16
).
When P5
7
(S
CLK22
) is selected as a clock I/O pin, S
RDY2
output
function is invalid, and P5
6
(S
CLK21
) is used as an I/O port.
_________
1/4
1/4
F/F
P5
6
/S
CLK21
P5
4
/R
X
D
P5
5
/T
X
D
P5
7
/S
RDY2
/
S
CLK22
“0”
“1”
“0”
“1”
X
IN
1/2
X
CIN
“1”
“0”
P5
7
/S
RDY2
/
S
CLK22
Serial I/O2 status register
Serial I/O2 control register
Receive buffer register
Address 001F
16
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Clock control circuit
Shift clock
Serial I/O2 synchronous clock selection bit
Baud rate generator
Address 0016
16
Division ratio 1/(n+1)
BRG count source selection bit
Clock control circuit
Falling edge detector
Transmit buffer register
Data bus
Address 001F
16
Shift clock
Transmit shift register shift
completion flag (TSC)
Transmit buffer empty flag (TBE)
Address 001E
16
Transmit interrupt request (TI)
Transmit interrupt source selection bit
Data bus
Address 001D
16
Transmit shift register
Serial I/O2 clock I/O pin selection bit
Internal system clock selection bit
BRG clock
switch bit
Serial I/O2
clock I/O pin
selection bit
D
7
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
0
D
1
D
2
D
3
D
4
D
5
D
6
RBF = 1
TSC = 1
Overrun error (OE)
detection
TBE = 0
TBE = 1
TSC = 0
Transmit/Receive shift clock
(1/2
—
1/2048 of internal
clock or external clock)
Serial I/O2 output TxD
Serial I/O2 input RxD
Write-in signal to serial I/O2 transmit/receive
buffer register (address 001F
16
)
Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting transmit interrupt source selection bit (TIC) of the serial I/O2
control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1.”
Receive enable signal
S
RDY2
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