
38B5 Group User’s Manual
APPLICATION
2-61
2.3 Serial I/O
Fig. 2.3.36 Registers setting relevant to reception side
1 1 1 1
1 1
SIO2CON
UART control register (address 001716)
UARTCON
Serial I/O2 clock: SCLK21
0
SIO2STS
Reception side
Serial I/O2 status register (address 001E16)
Receive buffer full flag
Confirm completion of receiving 1-byte data with this flag.
“1” : at completing reception
“0” : at reading out contents of Receive buffer register
Overrun error flag
“1” : When data is ready in Receive shift register while Receive buffer
register contains the data.
Serial I/O2 control register (address 001D16)
Synchronous clock: External clock input
SRDY2 output enabled
Transmit enabled
When using SRDY2 output, set this bit to “1”.
Receive disabled
Clock synchronous serial I/O
Serial I/O2 enabled