38B5 Group User’s Manual
1-22
HARDWARE
FUNCTIONAL DESCRIPTION
Fig. 15 Structure of interrupt related registers
Interrupt disable flag I
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
Fig. 14 Interrupt control
b7
b0
b7
b0
b7
b0
b7
b0
b7
b0
b7
b0
INT0 interrupt enable bit
INT1 interrupt enable bit
INT2 interrupt enable bit
Remote controller/counter overflow interrupt
enable bit
Serial I/O1 interrupt enable bit
Serial I/O automatic transfer interrupt enable bit
Timer X interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
INT0 interrupt request bit
INT1 interrupt request bit
INT2 interrupt request bit
Remote controller/counter overflow interrupt
request bit
Serial I/O1 interrupt request bit
Serial I/O automatic transfer interrupt request bit
Timer X interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
Interrupt edge selection register
INT0 interrupt edge selection bit
INT1 interrupt edge selection bit
INT2 interrupt edge selection bit
INT3 interrupt edge selection bit (Note 1)
INT4 interrupt edge selection bit
Not used (return "0" when read)
CNTR0 pin edge switch bit
CNTR1 pin edge switch bit (Note 1)
(INTEDGE : address 003A16)
0 : Falling edge active
1 : Rising edge active
Interrupt request register 1
Interrupt control register 1
0 : No interrupt request issued
1 : Interrupt request issued
(IREQ1 : address 003C16)
(ICON1 : address 003E16)
Interrupt request register 2
(IREQ2 : address 003D16)
Interrupt control register 2
0 : Interrupt disabled
1 : Interrupt enabled
(ICON2 : address 003F16)
Interrupt source switch register
INT3/serial I/O2 transmit interrupt switch bit (Note 1)
0 : INT3 interrupt
1 : Serial I/O2 transmit interrupt
INT4/AD conversion interrupt switch bit
0 : INT4 interrupt
1 : A-D conversion interrupt
Not used (return “0” when read)
(Do not write “1” to these bits.)
(IFR : address 003916)
0 : Rising edge count
1 : Falling edge count
INT3/serial I/O2 transmit interrupt enable bit (Note 3)
INT4 interrupt enable bit
AD conversion interrupt enable bit
FLD blanking interrupt enable bit
FLD digit interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit.)
INT3/serial I/O2 transmit interrupt request bit (Note 2)
INT4 interrupt request bit
AD conversion interrupt request bit
FLD blanking interrupt request bit
FLD digit interrupt request bit
Not used (returns “0” when read)
Timer 4 interrupt request bit (Note 2)
Timer 5 interrupt request bit
Timer 6 interrupt request bit
Serial I/O2 receive interrupt request bit
Timer 4 interrupt enable bit (Note 3)
Timer 5 interrupt enable bit
Timer 6 interrupt enable bit
Serial I/O2 receive interrupt enable bit
Notes 1: In the mask option type P, these bits are not available because CNTR1 function and INT3 function cannot be used.
2: In the mask option type P, if timer 4 interrupt whose count source is CNTR1 input and INT3 interrupt are selected, these bits do not become “1”.
3: In the mask option type P, timer 4 interrupt whose count source is CNTR1 input and INT3 interrupt are not available.