Addressing mode
Symbol
Function
Details
IMP
IMM
A
BIT, A
ZP
BIT, ZP
OP n
# OP n
#
OP n
#
3-86
APPENDIX
38B5 Group User’s Manual
3.11 Machine instructions
This instruction shifts either A or M one bit to
the right such that bit 7 of the result always is
set to 0, and the bit 0 is stored in C.
This instruction multiply Accumulator with the
memory specified by the Zero Page X address
mode and stores the high-order byte of the re-
sult on the Stack and the low-order byte in A.
This instruction adds one to the PC but does
no otheroperation.
When T = 0, this instruction transfers the con-
tents of A and M to the ALU which performs a
bit-wise “OR”, and stores the result in A.
When T = 1, this instruction transfers the con-
tents of M(X) and the M to the ALU which
performs a bit-wise OR, and stores the result
in M(X). The contents of A remain unchanged,
but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
This instruction pushes the contents of A to
the memory location designated by S, and
decrements the contents of S by one.
This instruction pushes the contents of PS to
the memory location designated by S and dec-
rements the contents of S by one.
This instruction increments S by one and
stores the contents of the memory designated
by S in A.
This instruction increments S by one and
stores the contents of the memory location
designated by S in PS.
This instruction shifts either A or M one bit left
through C. C is stored in bit 0 and bit 7 is
stored in C.
This instruction shifts either A or M one bit
right through C. C is stored in bit 7 and bit 0 is
stored in C.
This instruction rotates 4 bits of the M content
to the right.
This instruction increments S by one, and
stores the contents of the memory location
designated by S in PS. S is again incremented
by one and stores the contents of the memory
location designated by S in PCL. S is again
incremented by one and stores the contents of
memory location designated by S in PCH.
This instruction increments S by one and
stores the contents of the memory location
designated by S in PC L . S is again
incremented by one and the contents of the
memory location is stored in PCH. PC is
incremented by 1.
LSR
MUL
NOP
ORA
(Note 1)
PHA
PHP
PLA
PLP
ROL
ROR
RRF
RTI
RTS
M(S) A
← A V M(zz + X)
S
← S – 1
PC
← PC + 1
When T = 0
A
← A V M
When T = 1
M(X)
← M(X) V M
M(S)
← A
S
← S – 1
M(S)
← PS
S
← S – 1
S
← S + 1
A
← M(S)
S
← S + 1
PS
← M(S)
S
← S + 1
PS
← M(S)
S
← S + 1
PCL
← M(S)
S
← S + 1
PCH
← M(S)
S
← S + 1
PCL
← M(S)
S
← S + 1
PCH
← M(S)
(PC)
← (PC) + 1
7
0
←
←C ←
7
0
→
7
0
C →
→
7
0
→
→C
4A 2
1
EA 2
1
09 2
2
46
05
5
3
2
2A
6A
26
66
82
48
08
68
28
40
60
3
4
6
1
2
1
5
8
2