參數(shù)資料
型號(hào)： M38858MC-XXXHP
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁(yè)數(shù)： 42/105頁(yè)
文件大?。?/td> 1403K
代理商： M38858MC-XXXHP
38
3885 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 34 Structure of I2C control register
[I2C Control Register (S1D)] 001516
The I2C control register (S1D) controls data communication for-
mat.
Bits 0 to 2: Bit counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be
transmitted. The I2C interrupt request signal occurs immediately
after the number of count specified with these bits (ACK clock is
added to the number of count when ACK clock is selected by ACK
bit (bit 7 of S2)) have been transferred, and BC0 to BC2 are re-
turned to “0002”.
Also when a START condition is received, these bits become
“0002” and the address data is always transmitted and received in
8 bits.
Bit 3: I2C interface enable bit (ES0)
This bit enables to use the multi-master I2C BUS interface. When
this bit is set to “0”, the use disable status is provided, so that the
SDA and the SCL become high-impedance. When the bit is set to
“1”, use of the interface is enabled.
When ES0 = “0”, the following is performed.
PIN = “1”, BB = “0” and AL = “0” are set (which are bits of the I2C
status register at S1 ).
Writing data to the I2C data shift register (S0) is disabled.
Bit 4: Data format selection bit (ALS)
This bit decides whether or not to recognize slave addresses.
When this bit is set to “0”, the addressing format is selected, so
that address data is recognized. When a match is found between
a slave address and address data as a result of comparison or
when a general call (refer to “I2C Status Register”, bit 1) is re-
ceived, transfer processing can be performed. When this bit is set
to “1”, the free data format is selected, so that slave addresses are
not recognized.
Bit 5: Addressing format selection bit (10BIT SAD)
This bit selects a slave address specification format. When this bit
is set to “0”, the 7-bit addressing format is selected. In this case,
only the high-order 7 bits (slave address) of the I2C address regis-
ter (S0D) are compared with address data. When this bit is set to
“1”, the 10-bit addressing format is selected, and all the bits of the
I2C address register are compared with address data.
Bit 6: System clock stop selection bit (CLKSTP)
When executing the WIT or STP instruction, this bit selects the
condition of system clock provided to the multi-master I2C-BUS in-
terface. When this bit is set to “0”, system clock and operation of
the multi-master I2C-BUS interface stop by executing the WIT or
STP instruction.
When this bit is set to “1”, system clock and operation of the multi-
master I2C-BUS interface do not stop even when the WIT
instruction is executed.
When the system clock stop selection bit is “1”, do not execute the
STP instruction.
Bit 7: I2C-BUS interface pin input level selection bit
This bit selects the input level of the SCL and SDA pins of the multi-
master I2C-BUS interface.
b7
TISS
CLK
STP
10 BIT
SAD
ALS ES0 BC2 BC1 BC0
b0
System clock stop selection bit
0 : System clock stop
when executing WIT
or STP instruction
1 : Not system clock
stop when executing
WIT instruction
(Do not use the STP
instruction.)
I2C control register
(S1D : address 001516)
Bit counter (Number of
transmit/receive bits)
b2 b1 b0
00
0 : 8
00
1 : 7
01
0 : 6
01
1 : 5
10
0 : 4
10
1 : 3
11
0 : 2
11
1 : 1
I2C-BUS interface
enable bit
0 : Disabled
1 : Enabled
Data format selection bit
0 : Addressing format
1 : Free data format
Addressing format selection bit
0 : 7-bit addressing format
1 : 10-bit addressing format
I2C-BUS interface pin input
level selection bit
0 : CMOS input
1 : SMBUS input
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