參數(shù)資料
型號： M3851
廠商： Mitsubishi Electric Corporation
英文描述： Single Chip 8 Bits Microcomputer(8位單片機)
中文描述： 單芯片8位單片機（8位單片機）
文件頁數(shù)： 26/61頁
文件大小： 904K
代理商： M3851
26
3851 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 28 START/STOP condition detecting timing diagram
START/STOP Condition Detecting Operation
The START/STOP condition detection operations are shown in
Figures 28, 29, and Table 8. The START/STOP condition is set by
the START/STOP condition set bit.
The START/STOP condition can be detected only when the input
signal of the S
CL
and S
DA
pins satisfy three conditions: S
CL
re-
lease time, setup time, and hold time (see Table 8).
The BB flag is set to “1” by detecting the START condition and is
reset to “0” by detecting the STOP condition.
The BB flag set/reset timing is different in the standard clock mode
and the high-speed clock mode. Refer to Table 8, the BB flag set/
reset time.
Note:
When a STOP condition is detected in the slave mode (MST = 0), an
interrupt request signal “IICIRQ” occurs to the CPU.
START Condition Generating Method
When writing “1” to the MST, TRX, and BB bits of the I
2
C status
register (address 002D
16
) at the same time after writing the slave
address to the I
2
C data shift register (address 002B
16
) with the
condition in which the ES0 bit of the I
2
C control register (address
002E
16
) and the BB flag are “0”, a START condition occurs. After
that, the bit counter becomes “000
2
” and an S
CL
for 1 byte is out-
put. The START condition generating timing is different in the
standard clock mode and the high-speed clock mode. Refer to
Figure 26, the START condition generating timing diagram, and
Table 6, the START condition generating timing table.
STOP Condition Generating Method
When the ES0 bit of the I
2
C control register (address 002E
16
) is
“1,” write “1” to the MST and TRX bits, and write “0” to the BB bit
of the I
2
C status register (address 002D
16
) simultaneously. Then a
STOP condition occurs. The STOP condition generating timing is
different in the standard clock mode and the high-speed clock
mode. Refer to Figure 27, the STOP condition generating timing
diagram, and Table 7, the STOP condition generating timing table.
Fig. 26 START condition generating timing diagram
Fig. 27 STOP condition generating timing diagram
Table 7 STOP condition generating timing table
Item
Setup time
Hold time
4.5
μ
s (18 cycles)
Standard clock mode
5.0
μ
s (20 cycles)
Note:
Absolute time at
φ
= 4 MHz. The value in parentheses denotes the
number of
φ
cycles.
High-speed clock mode
3.0
μ
s (12 cycles)
2.5
μ
s (10 cycles)
Table 6 START condition generating timing table
Item
Setup time
Hold time
5.0
μ
s (20 cycles)
Standard clock mode
5.0
μ
s (20 cycles)
Note:
Absolute time at
φ
= 4 MHz. The value in parentheses denotes the
number of
φ
cycles.
High-speed clock mode
2.5
μ
s (10 cycles)
2.5
μ
s (10 cycles)
Table 8 START condition/STOP condition detecting conditions
Standard clock mode
SCC value + 1 cycle (6.25
μ
s)
Note:
Unit : Cycle number of system clock
φ
SSC value is the decimal notation value of the START/STOP condi-
tion set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC
value. The value in parentheses is an example when the I
2
C START/
STOP condition control register is set to “18
16
” at
φ
= 4 MHz.
Fig. 29 STOP condition detecting timing diagram
S
CL
release time
High-speed clock mode
4 cycles (1.0
μ
s)
2 cycles (1.0
μ
s)
2 cycles (0.5
μ
s)
3.5 cycles (0.875
μ
s)
SCC value + 1
2
SCC value + 1
2
SCC value –1
2
Setup time
Hold time
BB flag set/
reset time
cycle
< 4.0
μ
s (3.125
μ
s)
cycle
< 4.0
μ
s (3.125
μ
s)
+ 2 cycles (3.375
μ
s)
I
2
C status register
write signal
Hold time
Setup
time
S
CL
S
DA
I
2
C status register
write signal
Hold time
Setup
time
S
CL
S
DA
Hold time
Setup
time
S
CL
S
DA
BB flag
S
CL
release time
BB flag
reset
Hold time
Setup
time
S
CL
S
DA
BB flag
S
CL
release time
BB flag
reset
time
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