參數(shù)資料
型號(hào)： M38503G4A-XXXFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PDSO42
封裝： 8.40 X 17.5 MM, 0.80 MM PITCH, PLASTIC, SSOP-42
文件頁數(shù)： 43/59頁
文件大?。?/td> 885K
代理商： M38503G4A-XXXFP
Rev.2.13
Apr 17, 2009
Page 48 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Switching characteristics
NOTES:
1. When the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2. When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is “0”.
3. The XOUT pin is excluded.
NOTES:
1. When the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2. When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is “0”.
3. The XOUT pin is excluded.
Fig 47. Circuit for measuring output switching characteristics
Table 18
Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta =
20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Unit
Min.
Typ.
Max.
tWH(SCLK1)
Serial I/O1 clock output “H” pulse width
Fig. 47
tC(SCLK1)/2
30
ns
tWL(SCLK1)
Serial I/O1 clock output “L” pulse width
tC(SCLK1)/2
30
ns
td(SCLK1-TXD)
Serial I/O1 output delay time(1)
140
ns
tV(SCLK1-TXD)
Serial I/O1 output valid time(1)
30
ns
tr(SCLK1)
Serial I/O1 clock output rising time
30
ns
tf(SCLK1)
Serial I/O1 clock output falling time
30
ns
tWH(SCLK2)
Serial I/O2 clock output “H” pulse width
tC(SCLK2)/2
160
ns
tWL(SCLK2)
Serial I/O2 clock output “L” pulse width
tC(SCLK2)/2
160
ns
td(SCLK2-SOUT2)
Serial I/O2 output delay time(2)
200
ns
tV(SCLK2-SOUT2)
Serial I/O2 output valid time(2)
0ns
tf(SCLK2)
Serial I/O2 clock output falling time
30
ns
tr(CMOS)
CMOS output rising time(3)
10
30
ns
tf(CMOS)
CMOS output falling time(3)
10
30
ns
Table 19
Switching characteristics (2) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta =
20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Unit
Min.
Typ.
Max.
tWH(SCLK1)
Serial I/O1 clock output “H” pulse width
Fig. 47
tC(SCLK1)/2
50
ns
tWL(SCLK1)
Serial I/O1 clock output “L” pulse width
tC(SCLK1)/2
50
ns
td(SCLK1-TXD)
Serial I/O1 output delay time(1)
350
ns
tV(SCLK1-TXD)
Serial I/O1 output valid time(1)
30
ns
tr(SCLK1)
Serial I/O1 clock output rising time
50
ns
tf(SCLK1)
Serial I/O1 clock output falling time
50
ns
tWH(SCLK2)
Serial I/O2 clock output “H” pulse width
tC(SCLK2)/2
240
ns
tWL(SCLK2)
Serial I/O2 clock output “L” pulse width
tC(SCLK2)/2
240
ns
td(SCLK2-SOUT2)
Serial I/O2 output delay time(2)
400
ns
tV(SCLK2-SOUT2)
Serial I/O2 output valid time(2)
0ns
tf(SCLK2)
Serial I/O2 clock output falling time
50
ns
tr(CMOS)
CMOS output rising time(3)
20
50
ns
tf(CMOS)
CMOS output falling time(3)
20
50
ns
Measurement output pin
100pF
CMOS output
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