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參數(shù)資料
| 型號： | M38503E4SS |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 17/86頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | M38503E4SS |
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17
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
INTERRUPTS
Interrupts occur by 15 sources among 15 sources: six external,
eight internal, and one software.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the
corresponding interrupt request and enable bits are
“
1
”
and the in-
terrupt disable flag is
“
0
”
.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
(interrupt disable) flag disables all interrupts except the BRK in-
struction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
matically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
I
Notes
When the active edge of an external interrupt (INT
0
–
INT
3
, CNTR
0
,
CNTR
1
) is set, the corresponding interrupt request bit may also be
set. Therefore, take the following sequence:
1. Disable the interrupt
2. Change the interrupt edge selection register
(the timer XY mode register for CNTR
0
and CNTR
1
)
3. Clear the interrupt request bit to
“
0
”
4. Accept the interrupt.
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